CS5490-ISZ from Cirrus Logic, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	XOUT	passive	Crystal output for the external 4.096 MHz quartz crystal, which has an on-chip load capacitor; the datasheet says this pin is used for the crystal only.
2	XIN	input	Crystal input for the external 4.096 MHz quartz crystal, or external clock input supplying the system clock (MCLK) to the device.
3	RESET	input	Active-low Schmitt-trigger reset; assertion longer than 120 µs halts all operations and resets the hardware registers, and an external pull-up and decoupling capacitor are required.
4	IIN-	passive	Negative differential analog input of the current channel; full-scale differential input is ±50 mV at 50x gain and ±250 mV at 10x gain.
5	IIN+	passive	Positive differential analog input of the current channel; full-scale differential input is ±50 mV at 50x gain and ±250 mV at 10x gain.
6	VIN+	power_in	Positive differential analog input of the voltage channel with fixed 10x gain; full-scale signal is ±250 mV.
7	VIN-	power_in	Negative differential analog input of the voltage channel with fixed 10x gain; full-scale signal is ±250 mV.
8	VREF-	power_in	Return pin of the on-chip 2.4 V voltage reference; a 0.1 µF filter capacitor must be connected between VREF+ and VREF- and nothing else should be connected to these pins.
9	VREF+	power_in	Output of the on-chip 2.4 V voltage reference (limited drive capability); a 0.1 µF filter capacitor must be connected between VREF+ and VREF- and nothing else should be connected to these pins.
10	GNDA	power_in	Analog ground; the common-mode input range of the differential inputs is referenced from GNDA to VDDA.
11	VDDA	power_in	Positive analog supply, specified at 3.0 V to 3.6 V (3.3 V typical) with respect to GNDA.
12	DO	output	Configurable digital output for energy pulses, interrupt, energy direction, or zero-crossing signals, with VOH of VDDA-0.3 V at 10 mA and VOL of 0.5 V max at 12 mA.
13	TX	output	UART serial data output from the CS5490 to the host microcontroller (8-bit, LSB first, 10 bits per byte).
14	RX	input	UART serial data input to the CS5490 from the host microcontroller (8-bit, LSB first, 10 bits per byte).
15	MODE	input	Operating mode select that must be tied to VDDA for normal operation; it is used primarily for factory test procedures.
16	VDDD	passive	Decoupling pin for the internal digital supply; it is not a supply input for external circuitry.

Key specifications

Parameter	Value
Manufacturer	Cirrus Logic
Package	SOIC-16
Category	Data Converters
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Positive Analog Power Supply	VDDA	3	3.3	3.6	V		8
Specified Temperature Range	TA	-40		85	°C		8
DC Power Supplies	VDDA	-0.3		4	V	Note 15	14
Input Current	IIN	-10		10	mA	Notes 16 and 17	14
Input Current for Power Supplies		-50		50			14
Output Current	IOUT			100	mA	Note 18	14
Power Dissipation	PD			500	mW	Note 19	14
Input Voltage	VIN	-0.3			V	Note 20; max printed as (VDDA)+0.3	14
Junction-to-Ambient Thermal Impedance (2 Layer Board)	JA			140	°C/W	2 Layer Board	14
Junction-to-Ambient Thermal Impedance (4 Layer Board)	JA			70	°C/W	4 Layer Board	14
Ambient Operating Temperature	TA	-40		85	°C		14
Storage Temperature	Tstg	-65		150	°C		14
Active Energy Accuracy	PAvg	-0.1		0.1	%	All gain ranges; current dynamic range 4000:1; Notes 1 & 2	8
Reactive Energy Accuracy	QAvg	-0.1		0.1	%	All gain ranges; current dynamic range 4000:1; Notes 1 & 2	8
Apparent Power Accuracy	S	-0.1		0.1	%	All gain ranges; current dynamic range 1000:1; Notes 1 & 3	8
Current RMS Accuracy	IRMS	-0.1		0.1	%	All gain ranges; current dynamic range 1000:1; Notes 1, 3 & 4	8
Voltage RMS Accuracy	VRMS	-0.1		0.1	%	Voltage channel dynamic range 20:1; Notes 1 & 3	8
Power Factor Accuracy	PF	-0.1		0.1	%	All gain ranges; current dynamic range 1000:1; Notes 1 & 3	8
Common Mode Rejection Ratio (current channels)	CMRR	80			dB	DC, 50, 60Hz	10
Common Mode+Signal (current channels)		-0.25			V		10
Total Harmonic Distortion (current channels)	THD	90	100		dB	Gain = 50	10
Power Supply Rejection Ratio (current channels)	PSRR	60	65		dB	60Hz; Note 7; Gain = 10	10
Power Supply Rejection Ratio (current channels)	PSRR	68	75		dB	60Hz; Note 7; Gain = 50	10
Effective Input Impedance (current channels)	EII	30			k		10
Common Mode Rejection Ratio (voltage channels)	CMRR	80			dB	DC, 50, 60Hz	10
Common Mode+Signal (voltage channels)		-0.25			V		10
Total Harmonic Distortion (voltage channels)	THD	80	88		dB		10
Power Supply Rejection Ratio (voltage channels)	PSRR	60	65		dB	60Hz; Note 7; Gain = 10	10
Effective Input Impedance (voltage channels)	EII	2			M		10
Temperature Accuracy	T	-5		5	°C	After calibration (Note 6)	10
Reference Output Voltage	VREF	2.3	2.4	2.5	V		11
Master Clock (XIN) Frequency	MCLK	2.5	4.096	5	MHz	Internal gate oscillator	12
XIN Clock Duty Cycle		40		60	%		12
Phase Compensation Range		-10.79		10.79	°	60Hz, OWR = 4000Hz	12
Low-level Input Voltage (All Pins)	VIL			0.6	V		12
Low-level Output Voltage (DO)	VOL			0.5	V	DO, Iout = -12mA (Note 12)	12
Low-level Output Voltage (all other outputs)	VOL			0.5	V	All other outputs, Iout = -5mA	12
Input Leakage Current	Iin	-10		10	µA		12
3-state Leakage Current	IOZ	-10		10	µA		12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		3. This drawing conforms to JEDEC outline MS-012, variation AC for standard 16 SOIC narrow body. 4. Recommended reflow profile is per JEDEC/IPC J-STD-020.	56

CAD (KiCad official)

Symbol: CS5490-ISZ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: cs5490-isz-etched.step / cs5490-isz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs5490-isz.step / cs5490-isz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cirrus Logic datasheet (57 pp, sha256 d104b02dede6c2ff, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CS5490-ISZ

Verified CS5490-ISZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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