component
HC32L110C4PA-TSSOP20TR
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHC32L110C4PA-TSSOP20TR
XHSC · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
HC32L110C4PA-TSSOP20TR from XHSC, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P34 | bidirectional | General-purpose digital I/O P34, multiplexed with AIN4/VC4 analog input, PCA_CH0, LPUART_TXD, TIM5_CHA, TIM0_EXT, TIM4_CHA and RTC_1HZ output. |
| 2 | P35 | bidirectional | General-purpose digital I/O P35, multiplexed with AIN5/VC5 analog input, UART1_TXD, UART0_TXD, TIM6_CHB, TIM0_GATE, TIM4_CHB, SPI_MISO and I2C_SDA; the datasheet recommends reserving P35 and P36 as the ISP programming interface. |
| 3 | P36 | bidirectional | General-purpose digital I/O P36, multiplexed with AIN6/VC6/AVREF analog input (AVREF can serve as the external ADC reference), UART1_RXD, UART0_RXD, TIM6_CHA, PCA_CH4, TIM5_CHA, SPI_MOSI and I2C_SCL; the datasheet recommends reserving P35 and P36 as the ISP programming interface. |
| 4 | RESETB/P00 | input | Active-low chip reset input RESETB, with CMOS input thresholds, an always-on internal pull-up of about 80 kΩ and a 100 ns input filter; the pin can also be used as digital input P00. |
| 5 | P01 | bidirectional | General-purpose digital I/O P01, multiplexed with XTHI, the external high-speed crystal (4-32 MHz) clock input, AIN7/VC7 analog input, UART0_RXD, I2C_SDA, UART1_TXD, TIM0_TOG, TIM5_CHB, SPI_SCK, TIM2_EXT. |
| 6 | P02 | bidirectional | General-purpose digital I/O P02, multiplexed with XTHO, the external high-speed crystal oscillator output, AIN8 analog input, UART0_TXD, I2C_SCL, UART1_RXD, TIM0_TOGN, TIM6_CHA, SPI_CS and TIM2_GATE. |
| 7 | AVSS/DVSS | power_in | Chip ground for both the analog (AVSS) and digital (DVSS) domains, which must be connected to the external supply system within its allowed range. |
| 8 | VCAP | power_out | LDO core-supply output for internal circuits only, which requires a 4.7 µF capacitor connected and must not be used to power external circuits. |
| 9 | AVCC/DVCC | power_in | Chip supply input for the analog and digital domains, specified at 1.8 V to 5.5 V, with a decoupling capacitor placed close to the pin. |
| 10 | P03 | bidirectional | General-purpose digital I/O P03, multiplexed with LVDIN1 analog input (LVD monitor source), PCA_CH3, SPI_CS, TIM6_CHB, LPTIM_EXT, RTC_1HZ, PCA_ECI and VC0_OUT. |
| 11 | P15/XTLO | bidirectional | General-purpose digital I/O P15, multiplexed with XTLO, the 32.768 kHz low-speed crystal oscillator output, I2C_SDA, TIM2_TOG, TIM4_CHB, LPTIM_GATE, SPI_SCK, UART0_RXD and LVD_OUT. |
| 12 | P14/XTLI | bidirectional | General-purpose digital I/O P14, multiplexed with XTLI, the 32.768 kHz low-speed crystal oscillator input, I2C_SCL, TIM2_TOGN, PCA ECI, ADC_RDY, SPI_CS and UART0_TXD. |
| 13 | P23 | bidirectional | General-purpose digital I/O P23, multiplexed with LVDIN2/VC0 analog input, TIM6_CHA, TIM4_CHB, TIM4_CHA, PCA_CH0, SPI_MISO, UART1_TXD and IR_OUT (38 kHz carrier output). |
| 14 | P24 | bidirectional | General-purpose digital I/O P24, multiplexed with AIN0 analog input, TIM4_CHB, TIM5_CHB, HCLK_OUT, PCA_CH1, SPI_MOSI, UART1_RXD and VC1_OUT. |
| 15 | P25 | bidirectional | General-purpose digital I/O P25, multiplexed with LVDIN3/VC1 analog input, SPI_SCK, PCA_CH0, TIM5_CHA, LVD_OUT, LPUART_RXD, I2C_SDA and TIM1_GATE. |
| 16 | P26 | bidirectional | General-purpose digital I/O P26, multiplexed with AIN1 analog input, SPI_MOSI, TIM4_CHA, TIM5_CHB, PCA_CH2, LPUART_TXD, I2C_SCL and TIM1_EXT. |
| 17 | P27 | bidirectional | General-purpose digital I/O P27, which is also the SWD debug data pin SWDIO and one of the two pins (with P31) used for the SWD programming interface. |
| 18 | P31 | bidirectional | General-purpose digital I/O P31, which is also the SWD debug clock pin SWCLK and one of the two pins (with P27) used for the SWD programming interface. |
| 19 | P32 | bidirectional | General-purpose digital I/O P32, multiplexed with AIN2/VC2 analog input, TIM3_TOGN, PCA_CH2, TIM6_CHB, VC1OUT, UART1_TXD, PCA_CH4 and RTC_1HZ. |
| 20 | P33 | bidirectional | General-purpose digital I/O P33, multiplexed with AIN3/VC3 analog input, LPUART_RXD, PCA_CH1, TIM5_CHB, PCA_ECI, UART1_RXD, XTL_OUT (32K oscillator output) and TIM1_TOGN. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage (incl. AVCC and DVCC) | VCC, VSS | -0.3 | 5.5 | V | 28 | ||
| Voltage difference between supply pins | /ΔVCCx/ | 50 | mV | 28 | |||
| Voltage difference between ground pins | /VSSx, VSS/ | 50 | mV | 28 | |||
| Total current through DVCC/AVCC supply lines (supply current) | IVCC | 300 | mA | 28 | |||
| Total current through VSS ground line (sink current) | IVSS | 300 | mA | 28 | |||
| Output sink current on any I/O and control pin | IIO | 25 | mA | 28 | |||
| Output current on any I/O and control pin | -25 | mA | 28 | ||||
| Injection current, RESETB pin | IINJ(PIN) | -5 | 5 | mA | 28 | ||
| Injection current, XTHI and XTLI pins | IINJ(PIN) | -5 | 5 | mA | 28 | ||
| Injection current, other pins | IINJ(PIN) | -5 | 5 | mA | 28 | ||
| Sum of injection current, all I/O and control pins | ∑IINJ(PIN) | -25 | 25 | mA | 28 | ||
| External input voltage range (LVD) | Vex | 0 | V | 32 | |||
| Internal 2.5V reference voltage | VREF25 | 2.475 | 2.5 | 2.525 | V | TA=25°C, VCC=3.3V | 33 |
| Internal 2.5V reference voltage | VREF25 | 2.463 | 2.5 | 2.525 | V | TA=-40 to 85°C, VCC=2.8 to 5.5V | 33 |
| Internal 1.5V reference voltage | VREF15 | 1.485 | 1.5 | 1.515 | V | TA=25°C, VCC=3.3V | 33 |
| Internal 1.5V reference voltage | VREF15 | 1.477 | 1.5 | 1.519 | V | TA=-40 to 85°C, VCC=1.8 to 5.5V | 33 |
| IDD run mode, RCH 4M | IDD | 700 | 880 | μA | All peripherals clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 4M | 33 | |
| IDD run mode, RCH 8M | IDD | 1350 | 1600 | μA | All peripherals clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 8M | 33 | |
| IDD run mode, RCH 16M | IDD | 2500 | 3000 | μA | All peripherals clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 16M | 33 | |
| IDD run mode, RCH 24M | IDD | 3600 | 4300 | μA | All peripherals clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 24M | 34 | |
| IDD run while(1) in flash, RCH 4M | IDD | 550 | 750 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 4M | 34 | |
| IDD run while(1) in flash, RCH 8M | IDD | 1050 | 1300 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 8M | 34 | |
| IDD run while(1) in flash, RCH 16M | IDD | 1900 | 2400 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 16M | 34 | |
| IDD run while(1) in flash, RCH 24M | IDD | 2700 | 3300 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 24M | 34 | |
| IDD run while(1) in flash, RCH 32M (flash wait=1) | IDD | 2850 | 3000 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 32M (Flash Wait=1) | 34 | |
| IDD sleep mode, peripheral clock ON, RCH 4M | IDD | 260 | 280 | μA | All peripheral clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 4M | 34 | |
| IDD sleep mode, peripheral clock ON, RCH 8M | IDD | 500 | 520 | μA | All peripheral clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 8M | 34 | |
| IDD sleep mode, peripheral clock ON, RCH 16M | IDD | 950 | 970 | μA | All peripheral clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 16M | 34 | |
| IDD sleep mode, peripheral clock ON, RCH 24M | IDD | 1400 | 1420 | μA | All peripheral clock ON; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 24M | 34 | |
| IDD sleep mode, peripheral clock OFF, RCH 4M | IDD | 110 | 125 | μA | All peripheral clock OFF; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 4M | 34 | |
| IDD sleep mode, peripheral clock OFF, RCH 8M | IDD | 190 | 210 | μA | All peripheral clock OFF; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 8M | 34 | |
| IDD sleep mode, peripheral clock OFF, RCH 16M | IDD | 330 | 360 | μA | All peripheral clock OFF; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 16M | 34 | |
| IDD sleep mode, peripheral clock OFF, RCH 24M | IDD | 470 | 500 | μA | All peripheral clock OFF; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 24M | 34 | |
| IDD sleep mode, peripheral clock OFF, RCH 32M | IDD | 580 | 610 | μA | All peripheral clock OFF; VCAP=1.55V; VCC=1.8-5.5V; RCH clock source; 32M | 34 | |
| IDD LP run, all peripherals ON, XTL 32.768kHz | IDD | 7 | 9 | μA | All peripherals clock ON, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=-40 to 25°C | 34 | |
| IDD LP run, all peripherals ON, XTL 32.768kHz | IDD | 7.3 | 9.2 | μA | All peripherals clock ON, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=50°C | 34 | |
| IDD LP run, all peripherals ON, XTL 32.768kHz | IDD | 8.9 | 11.3 | μA | All peripherals clock ON, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=85°C | 34 | |
| IDD LP run, all peripherals OFF, XTL 32.768kHz | IDD | 6 | 8 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=-40 to 25°C | 34 | |
| IDD LP run, all peripherals OFF, XTL 32.768kHz | IDD | 6.1 | 8.2 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=50°C | 34 | |
| IDD LP run, all peripherals OFF, XTL 32.768kHz | IDD | 7.7 | 10.1 | μA | All peripheral clock OFF, run while(1) in Flash; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=85°C | 34 | |
| IDD LP sleep, all peripherals ON, XTL 32.768kHz | IDD | 3.3 | 3.5 | μA | All peripheral clock ON; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=-40 to 25°C | 34 | |
| IDD LP sleep, all peripherals ON, XTL 32.768kHz | IDD | 3.6 | 3.8 | μA | All peripheral clock ON; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=50°C | 34 | |
| IDD LP sleep, all peripherals ON, XTL 32.768kHz | IDD | 5.4 | 5.8 | μA | All peripheral clock ON; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=85°C | 34 | |
| IDD LP sleep, peripherals OFF except LPTimer and RTC, XTL 32.768kHz | IDD | 2.2 | 2.4 | μA | All peripheral clock OFF except LPTimer and RTC; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=-40 to 25°C | 34 | |
| IDD LP sleep, peripherals OFF except LPTimer and RTC, XTL 32.768kHz | IDD | 2.5 | 2.6 | μA | All peripheral clock OFF except LPTimer and RTC; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=50°C | 34 | |
| IDD LP sleep, peripherals OFF except LPTimer and RTC, XTL 32.768kHz | IDD | 4.2 | 4.6 | μA | All peripheral clock OFF except LPTimer and RTC; VCAP=1.55V; VCC=1.8-5.5V; XTL 32.768kHz (Driver=1); TA=85°C | 34 | |
| IDD deep sleep, peripherals OFF except RTC and WDT | IDD | 1.5 | 1.65 | μA | All peripheral clock OFF except RTC, WDT; VCAP=1.55V; VCC=1.8-5.5V; TA=-40 to 25°C | 34 | |
| IDD deep sleep, peripherals OFF except RTC and WDT | IDD | 1.85 | 2.2 | μA | All peripheral clock OFF except RTC, WDT; VCAP=1.55V; VCC=1.8-5.5V; TA=50°C | 34 | |
| IDD deep sleep, peripherals OFF except RTC and WDT | IDD | 3.5 | 4.2 | μA | All peripheral clock OFF except RTC, WDT; VCAP=1.55V; VCC=1.8-5.5V; TA=85°C | 34 |
CAD (KiCad official)
- Symbol:
HC32L110C4PA-TSSOP20TR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
hc32l110c4pa-tssop20tr-etched.step/hc32l110c4pa-tssop20tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32l110c4pa-tssop20tr.step/hc32l110c4pa-tssop20tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (69 pp, sha256
9ca08dbf01e4bbb9, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).