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CW32L031C8U6
Public Made by Adomby adom
CW Microcontrollers (MCU/MPU/SOC), QFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCW32L031C8U6
CW · Microcontrollers (MCU/MPU/SOC) · QFN-48(7x7)
CW32L031C8U6 from CW, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vcore | power_out | Internal core-logic supply node fed by the on-chip regulator; the extracted text gives no voltage limit or external capacitor value for this pin. |
| 2 | PC13 | bidirectional | Standard I/O (TC) with alternate functions UART1_TXD, RTC_1Hz, UART1_CTS, RTC_OUT, BTIM_ETR and RTC_TAMP; sinks/sources up to ±8 mA (up to ±20 mA where VOH/VOL requirements are relaxed). |
| 3 | PC14 | bidirectional | Standard I/O (TC) with alternate functions AWT_ETR, UART2_TXD, UART1_RTS, BTIM2_TOGN and UART2_RXD, and the 32.768 kHz LSE oscillator input OSC32_IN; sinks/sources up to ±8 mA. |
| 4 | PC15 | bidirectional | Standard I/O (TC) with alternate functions HSE_OUT, UART2_RXD, MCO_OUT, BTIM2_TOGP, UART2_TXD and UART1_RXD, and the LSE oscillator output OSC32_OUT; sinks/sources up to ±8 mA. |
| 5 | PF00 | bidirectional | Standard I/O (TC) with alternate functions AWT_ETR, UART3_TXD, I2C_SDA, BTIM1_TOGN, UART3_RXD and GTIM2_TOGP, and the HSE oscillator input OSC_IN (4-32 MHz crystal or 1-32 MHz external clock in bypass mode). |
| 6 | PF01 | bidirectional | Standard I/O (TC) with alternate functions LSE_OUT, UART3_RXD, I2C_SCL, BTIM1_TOGP, UART3_TXD and GTIM2_TOGN, and the HSE oscillator output OSC_OUT; sinks/sources up to ±8 mA. |
| 7 | NRST | input | Active-low chip reset input with internal pull-up of 7-9 kΩ (8 kΩ typical); VIL max 0.3·VDD, VIH min 0.7·VDD, and minimum reset pulse width 20 µs. |
| 8 | VSSA | power_in | Analog ground. |
| 9 | VDDA | power_in | Analog supply for the ADC, reset circuit and internal RC oscillators; operating range 1.65 V to 5.5 V and must always be greater than or equal to VDD. |
| 10 | PA00 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN0, VC1_CH0 and LVD_CH1, and digital alternate functions UART3_CTS, UART2_CTS, RTC_TAMP, VC1_OUT, GTIM2_CH1 and GTIM2_ETR; injection current limit ±5 mA. |
| 11 | PA01 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN1 and VC1_CH1, and digital alternate functions UART3_RTS, UART2_RTS, LVD_OUT, GTIM2_CH2 and RTC_TAMP; injection current limit ±5 mA. |
| 12 | PA02 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN2 and VC1_CH2, and digital alternate functions UART3_TXD, UART2_TXD, VC2_OUT, GTIM2_CH3 and AWT_ETR; injection current limit ±5 mA. |
| 13 | PA03 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN3 and VC1_CH3, and digital alternate functions UART3_RXD, UART2_RXD, GTIM2_CH2, PCLK_OUT, UART3_TXD, GTIM2_CH4 and ATIM_CH3A; injection current limit ±5 mA. |
| 14 | PA04 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN4 and VC1_CH4, and digital alternate functions MCO_OUT, UART2_CTS, HCLK_OUT, SPI_CS, GTIM2_ETR and ATIM_CH2A; injection current limit ±5 mA. |
| 15 | PA05 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN5, VC1_CH5 and VC2_CH0, and digital alternate functions GTIM2_ETR, UART2_RTS, BTIM2_TOGN, SPI_SCK, GTIM2_CH1 and ATIM_CH1A; injection current limit ±5 mA. |
| 16 | PA06 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN6, VC1_CH6 and VC2_CH1, and digital alternate functions UART2_RXD, UART2_TXD, VC1_OUT, BTIM2_TOGP, SPI_MISO, GTIM1_CH1 and ATIM_BK; injection current limit ±5 mA. |
| 17 | PA07 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN7, VC1_CH7 and VC2_CH2, and digital alternate functions UART2_TXD, UART2_RXD, VC2_OUT, BTIM1_TOGN, SPI_MOSI, GTIM1_CH2 and ATIM_CH1B; injection current limit ±5 mA. |
| 18 | PB00 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN8/ExRef (external ADC reference), VC2_CH3 and LVD_CH2, and digital alternate functions UART2_RXD, UART1_CTS, UART2_TXD, BTIM1_TOGP, HSIOSC_OUT, GTIM1_CH3 and ATIM_CH2B; injection current limit ±5 mA. |
| 19 | PB01 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN9 and VC2_CH4, and digital alternate functions UART2_TXD, UART1_RTS, UART2_RXD, BTIM3_TOGN, GTIM1_CH4 and ATIM_CH3B; injection current limit ±5 mA. |
| 20 | PB02 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN10 and VC2_CH5, and digital alternate functions UART2_CTS, UART1_TXD, HSE_OUT, UART1_RXD, BTIM3_TOGP, GTIM1_ETR and ATIM_CH1A; injection current limit ±5 mA. |
| 21 | PB10 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN11 and VC2_CH6, and digital alternate functions UART2_RTS, UART1_RXD, I2C_SCL, UART1_TXD, GTIM2_CH3 and ATIM_CH2A; injection current limit ±5 mA. |
| 22 | PB11 | bidirectional | Analog-capable I/O (TTa) with analog functions ADC_IN12, VC2_CH7 and LVD_CH3, and digital alternate functions LSI_OUT, I2C_SDA, BTIM_ETR, GTIM2_CH4 and ATIM_CH3A; injection current limit ±5 mA. |
| 23 | VSS | power_in | Ground reference for the digital supply domain. |
| 24 | VDD | power_in | Digital supply for the I/O ports and internal regulator, 1.65 V to 5.5 V; all VDD pins must be powered at the same voltage. |
| 25 | PB12 | bidirectional | Standard I/O (TC) with alternate functions GTIM2_TOGP, LSE_OUT, SPI_CS, GTIM1_TOGP and ATIM_BK; sinks/sources up to ±8 mA. |
| 26 | PB13 | bidirectional | Standard I/O (TC) with alternate functions GTIM2_TOGN, SPI_SCK, GTIM1_TOGN and ATIM_CH1B; sinks/sources up to ±8 mA. |
| 27 | PB14 | bidirectional | Standard I/O (TC) with alternate functions GTIM2_CH1, SPI_MISO, RTC_OUT and ATIM_CH2B; sinks/sources up to ±8 mA. |
| 28 | PB15 | bidirectional | Standard I/O (TC) with alternate functions GTIM2_CH2, BTIM2_TOGN, SPI_MOSI, RTC_1Hz and ATIM_CH3B; sinks/sources up to ±8 mA. |
| 29 | PA08 | bidirectional | Standard I/O (TC) with alternate functions UART1_TXD, BTIM2_TOGP, MCO_OUT, LVD_OUT and ATIM_CH1A; sinks/sources up to ±8 mA. |
| 30 | PA09 | bidirectional | Standard I/O (TC) with alternate functions UART3_TXD, UART1_RXD, I2C_SCL, BTIM1_TOGN, SPI_CS, UART3_RXD and ATIM_CH2A; sinks/sources up to ±8 mA. |
| 31 | PA10 | bidirectional | Standard I/O (TC) with alternate functions UART3_RXD, UART1_CTS, I2C_SDA, BTIM1_TOGP, SPI_SCK, UART3_TXD and ATIM_CH3A; sinks/sources up to ±8 mA. |
| 32 | PA11 | bidirectional | Standard I/O (TC) with alternate functions UART3_CTS, UART1_RTS, VC1_OUT, SPI_MISO and ATIM_GATE; sinks/sources up to ±8 mA. |
| 33 | PA12 | bidirectional | Standard I/O (TC) with alternate functions UART3_RTS, BTIM_ETR, VC2_OUT, SPI_MOSI and ATIM_ETR; sinks/sources up to ±8 mA. |
| 34 | PA13/SWDIO | bidirectional | Standard I/O (TC) with alternate functions I2C_SDA, UART1_RXD, UART2_TXD and IR_OUT; after reset it serves as the SWD data pin SWDIO with internal pull-up enabled. |
| 35 | PF06 | bidirectional | Standard I/O (TC) with alternate functions UART3_CTS, I2C_SCL, UART2_CTS and BTIM3_TOGN; sinks/sources up to ±8 mA. |
| 36 | PF07 | bidirectional | Standard I/O (TC) with alternate functions UART3_RTS, I2C_SDA, UART2_RTS and BTIM3_TOGP; sinks/sources up to ±8 mA. |
| 37 | PA14/SWCLK | bidirectional | Standard I/O (TC) with alternate functions UART3_TXD, I2C_SCL, UART1_TXD and UART2_RXD; after reset it serves as the SWD clock SWCLK with internal pull-up enabled. |
| 38 | PA15 | bidirectional | Standard I/O (TC) with alternate functions UART3_RXD, GTIM2_CH1, UART1_RXD, UART2_RXD, SPI_CS, GTIM2_ETR and ATIM_CH1B; sinks/sources up to ±8 mA. |
| 39 | PB03 | bidirectional | Standard I/O (TC) with alternate functions UART3_RTS, GTIM2_CH2, UART1_CTS, UART2_TXD, SPI_SCK, GTIM1_ETR and ATIM_CH2B; sinks/sources up to ±8 mA. |
| 40 | PB04 | bidirectional | Standard I/O (TC) with alternate functions UART3_CTS, UART1_RTS, UART2_CTS, SPI_MISO, GTIM1_CH1 and ATIM_CH3B; sinks/sources up to ±8 mA. |
| 41 | PB05 | bidirectional | Standard I/O (TC) with alternate functions AWT_ETR, UART2_RTS, SPI_MOSI, GTIM1_CH2 and ATIM_CH1A; sinks/sources up to ±8 mA. |
| 42 | PB06 | bidirectional | Standard I/O (TC) with alternate functions UART3_TXD, UART3_RXD, I2C_SCL, GTIM1_TOGP and ATIM_CH2A; sinks/sources up to ±8 mA. |
| 43 | PB07 | bidirectional | Standard I/O (TC) with alternate functions UART3_RXD, UART3_TXD, I2C_SDA, GTIM1_TOGN and ATIM_CH3A; sinks/sources up to ±8 mA. |
| 44 | PF03/BOOT | input | BOOT pin (structure B) sampled at startup to select between the internal bootloader and the user program. |
| 45 | PB08 | bidirectional | Standard I/O (TC) with alternate functions I2C_SCL, UART1_RXD, UART1_TXD, GTIM1_CH3 and ATIM_ETR; sinks/sources up to ±8 mA. |
| 46 | PB09 | bidirectional | Standard I/O (TC) with alternate functions I2C_SDA, UART1_TXD, UART1_RXD, IR_OUT, GTIM1_CH4 and ATIM_BK; sinks/sources up to ±8 mA. |
| 47 | VSS | power_in | Ground reference for the digital supply domain. |
| 48 | VDD | power_in | Digital supply for the I/O ports and internal regulator, 1.65 V to 5.5 V; all VDD pins must be powered at the same voltage. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CW |
| Package | QFN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage (VDD-VSS) | VDD - VSS | -0.3 | 6 | V | 35 | ||
| External analog supply voltage (VDDA-VSS) | VDDA-VSS | -0.3 | 6 | V | 35 | ||
| Maximum allowed VDD over VDDA difference | VDD-VDDA | 0.3 | V | VDD greater than VDDA | 35 | ||
| Difference between different VDD pins | /ΔVDDx/ | 0.05 | V | 35 | |||
| Difference between different VSS pins | /VSSX-VSS/ | 0.05 | V | 35 | |||
| Total sink current into all VDD supply lines | ΣIVDD | 120 | mA | 35 | |||
| Total source current from all VSS supply lines | ΣIVSS | -120 | mA | 35 | |||
| Sink current of a single VDD supply line | IVDD(PIN) | 100 | mA | 35 | |||
| Source current of a single VSS supply line | IVSS(PIN) | -100 | mA | 35 | |||
| Sink current of a single I/O or control pin | IIO(PIN) | 25 | mA | 35 | |||
| Source current of a single I/O or control pin | IIO(PIN) | -25 | mA | 35 | |||
| Total sink current of all I/O and control pins | ΣIIO(PIN) | 80 | mA | 35 | |||
| Total source current of all I/O and control pins | ΣIIO(PIN) | -80 | mA | 35 | |||
| Injection current on TC and RST pins | IINJ(PIN) | -5 | 5 | mA | 35 | ||
| Injection current on TTa pins | IINJ(PIN) | -5 | 5 | mA | 35 | ||
| Total injection current of all I/O and control pins | ΣIINJ(PIN) | -25 | 25 | mA | 35 | ||
| ESD voltage, human body model | VESD(HBM) | 8 | kV | TA=+25℃, conforms to JESD22-A115C | 48 | ||
| ESD voltage, charged device model | VESD(CDM) | 2 | kV | TA=+25℃, conforms to JESD22-A115C | 48 | ||
| Storage temperature range | TSTG | -65 | 150 | ℃ | 36 | ||
| Maximum junction temperature | TJ | 105 | ℃ | 36 | |||
| Internal AHB bus frequency fHCLK | fHCLK | 0 | 48 | MHz | VDD ≥ 1.8V | 37 | |
| Internal APB bus frequency fPCLK | fPCLK | 0 | 48 | MHz | VDD ≥ 1.8V | 37 | |
| Internal AHB bus frequency fHCLK | fHCLK | 0 | 24 | MHz | 1.65V ≤ VDD < 1.8V | 37 | |
| Internal APB bus frequency fPCLK | fPCLK | 0 | 24 | MHz | 1.65V ≤ VDD < 1.8V | 37 | |
| Standard operating voltage | VDD | 1.65 | 5.5 | V | 37 | ||
| Analog operating voltage | VDDA | 1.65 | 5.5 | V | 须等于 VDD | 37 | |
| I/O input voltage (TC I/O), lower limit | VIN | -0.3 | V | TC I/O | 37 | ||
| I/O input voltage (TTa I/O), lower limit | VIN | -0.3 | V | TTa I/O | 37 | ||
| BOOT input voltage, lower limit | VIN | -0.3 | V | BOOT | 37 | ||
| Ambient temperature TA (maximum power dissipation) | TA | -40 | 85 | ℃ | 最大功率耗散, temperature label 6 | 37 | |
| Ambient temperature TA (low power dissipation) | TA | -40 | 105 | ℃ | 低功率耗散, temperature label 6 | 37 | |
| Junction temperature range TJ | TJ | -40 | 105 | ℃ | temperature label 6 | 37 | |
| VDD rise rate | tVDD | 0 | μs/V | 37 | |||
| VDD fall rate | tVDD | 20 | μs/V | 37 | |||
| VDDA rise rate | tVDDA | 0 | μs/V | 37 | |||
| VDDA fall rate | tVDDA | 20 | μs/V | 37 | |||
| POR/BOR threshold, falling edge | VPOR/BOR | 1.451 | 1.5 | 1.552 | V | 下降沿 | 38 |
| POR/BOR threshold, rising edge | VPOR/BOR | 1.502 | 1.55 | 1.6 | V | 上升沿 | 38 |
| BOR hysteresis | VBORhyst | 50 | mV | 38 | |||
| Reset duration | tRSTTEMPO | 4 | 6.5 | 13 | ms | 38 | |
| Internal 1.5V reference voltage | VREFINT1V5 | 1.485 | 1.5 | 1.515 | V | -40℃ < TA < +85℃ | 38 |
| Internal 2.5V reference voltage | VREFINT2V5 | 2.475 | 2.5 | 2.525 | V | -40℃ < TA < +85℃ | 38 |
| Internal reference voltage distribution over full temperature range | ΔVREFINT | 101 | mV | VDDA = 3V | 38 | ||
| Internal reference temperature coefficient | TCoeff | -601 | 601 | ppm/℃ | 38 | ||
| Run mode supply current from FLASH, all peripherals on, 48MHz | IDD | 7.2 | 8.2 | mA | VDD=VDDA=5.5V, TA=85℃, HSI or HSE, 48MHz, code in FLASH, all peripherals on | 39 | |
| Run mode supply current from FLASH, all peripherals off, 48MHz | IDD | 4.6 | 5.2 | mA | VDD=VDDA=5.5V, TA=85℃, HSI or HSE, 48MHz, code in FLASH, all peripherals off | 39 | |
| Run mode supply current from RAM, all peripherals on, 48MHz | IDD | 5.3 | 5.9 | mA | VDD=VDDA=5.5V, TA=85℃, HSI or HSE, 48MHz, code in RAM, all peripherals on | 39 | |
| Run mode supply current from RAM, all peripherals off, 48MHz | IDD | 2.6 | 2.9 | mA | VDD=VDDA=5.5V, TA=85℃, HSI or HSE, 48MHz, code in RAM, all peripherals off | 39 | |
| Sleep mode supply current, all peripherals on, 48MHz | IDD | 3.8 | 4.2 | mA | VDD=VDDA=5.5V, TA=85℃, HSI or HSE, 48MHz, code in FLASH or RAM, all peripherals on | 39 | |
| Sleep mode supply current, all peripherals off, 48MHz | IDD | 1.1 | 1.23 | mA | VDD=VDDA=5.5V, TA=85℃, HSI or HSE, 48MHz, code in FLASH or RAM, all peripherals off | 39 | |
| DeepSleep supply current, regulator in run mode, all oscillators off | IDD | 0.45 | 3.84 | μA | VDD=VDDA=3.6V, TA=85℃, regulator in run mode, all oscillators off | 40 | |
| DeepSleep supply current, regulator in run mode, LSI and IWDT on | IDD | 1.11 | 4.65 | μA | VDD=VDDA=3.6V, TA=85℃, regulator in run mode, LSI and IWDT on | 40 | |
| HSE oscillator frequency | fOSC_IN | 4 | 8 | 32 | MHz | 45 | |
| HSI factory calibration accuracy | ACCHSI | -2 | 2 | % | TA = -40℃ ~ +85℃ | 46 | |
| Weak pull-up equivalent resistance (I/O) | RPU | 45 | 75 | 220 | kΩ | VIN = VSS | 48 |
| Weak pull-down equivalent resistance (I/O) | RPD | 16 | 30 | 50 | kΩ | VIN = VDDIOx | 48 |
| High-level output voltage | VOH | 3.02 | V | Sourcing 10mA, VDD = 3.3V | 49 | ||
| Low-level output voltage | VOL | 0.23 | V | Sinking 10mA, VDD = 3.3V | 49 | ||
| NRST pull-up equivalent resistance | RPU | 7 | 8 | 9 | kΩ | VIN = VSS | 51 |
| ADC comprehensive error ET | ET | -3 | 2.5 | 3 | LSB | fADC = 24MHz, VDDA = 1.65V |
53 |
CAD (KiCad official)
- Symbol:
CW32L031C8U6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
cw32l031c8u6-etched.step/cw32l031c8u6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cw32l031c8u6.step/cw32l031c8u6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CW datasheet (74 pp, sha256
0e51efc1f45a11c9, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).