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CD4021BPWR
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4021BPWR
Texas Instruments · Shift Registers · TSSOP-16
CD4021BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PI-8 | input | Parallel (jam) data input to register stage 8; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high (CD4021B). |
| 2 | Q6 | output | Buffered Q output tapped from internal register stage 6. |
| 3 | Q8 | output | Buffered Q output from the final register stage 8 (main serial data output). |
| 4 | PI-4 | input | Parallel (jam) data input to register stage 4; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |
| 5 | PI-3 | input | Parallel (jam) data input to register stage 3; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |
| 6 | PI-2 | input | Parallel (jam) data input to register stage 2; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |
| 7 | PI-1 | input | Parallel (jam) data input to register stage 1; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |
| 8 | VSS | power_in | Negative supply / ground return; supply-voltage range VDD to VSS is 3 V to 18 V over the full package-temperature range. |
| 9 | PARALLEL/SERIAL CONTROL | input | Mode control input: when high, data is asynchronously jammed into the 8-stage register via the parallel inputs; when low, data is shifted in serially, synchronous with the clock's positive transition. |
| 10 | CLOCK | input | Clock input; register shifts on the positive transition, with maximum clock frequency 3 MHz at VDD=5V, 6 MHz at 10V, and 8.5 MHz at 15V per the recommended operating conditions. |
| 11 | SERIAL IN | input | Single serial data input; data is shifted into the 8-stage register synchronously with the positive clock transition when PARALLEL/SERIAL CONTROL is low. |
| 12 | Q7 | output | Buffered Q output tapped from internal register stage 7. |
| 13 | PI-5 | input | Parallel (jam) data input to register stage 5; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |
| 14 | PI-6 | input | Parallel (jam) data input to register stage 6; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |
| 15 | PI-7 | input | Parallel (jam) data input to register stage 7; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |
| 16 | VDD | power_in | Positive supply pin; supply-voltage range VDD to VSS is 3 V to 18 V over the full package-temperature range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4021BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4021bpwr-etched.step/cd4021bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4021bpwr.step/cd4021bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
89a926918808a607, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-5(vision), consensusclaude-opus-4-8(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).