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JHT1302ARZ
Public Made by Adomby adom
JYJE Real Time Clocks, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownJHT1302ARZ
JYJE · Real Time Clocks · SOP-8
JHT1302ARZ from JYJE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC2 | power_in | Primary power-supply pin in the dual-supply configuration; the device runs from the larger of VCC1 or VCC2, and VCC2 powers the device when it is greater than VCC1 + 0.2V. |
| 2 | X1 | passive | Connection for a standard 32.768kHz quartz crystal specified at 6pF load capacitance, or the input for an external 32.768kHz oscillator signal. |
| 3 | X2 | passive | Second connection for the 32.768kHz quartz crystal, which is left floating when X1 is driven by an external oscillator. |
| 4 | GND | power_in | Ground reference pin for the device. |
| 5 | CE | input | Chip-enable input that must be asserted high during any read or write, with an internal 40kΩ (typ) pulldown to ground. |
| 6 | I/O | bidirectional | Bidirectional data pin of the 3-wire serial interface (input or push-pull output), with an internal 40kΩ (typ) pulldown to ground. |
| 7 | SCLK | input | Serial clock input that synchronizes data movement on the serial interface, with an internal 40kΩ (typ) pulldown to ground. |
| 8 | VCC1 | power_in | Low-power backup supply pin for single-supply, battery, or super-cap operation and trickle charging, UL recognized to guard against reverse charging current with lithium batteries. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JYJE |
| Package | SOP-8 |
| Category | Clock/Timing |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC1, VCC2 | 2 | 3.3 | 5.5 | V | VCC1, VCC2 (Notes 2, 10) | 10 |
| Logic 1 Input | VIH | 2 | V | (Note 2) | 10 | ||
| Logic 0 Input | VIL | -0.3 | 0.3 | V | VCC = 2.0V (Note 2) | 10 | |
| Logic 0 Input | VIL | -0.3 | 0.8 | V | VCC = 5V | 10 | |
| Input Leakage | ILI | 85 | 500 | A | (Notes 5, 13) | 10 | |
| I/O Leakage | ILO | 85 | 500 | A | (Notes 5, 13) | 10 | |
| Logic 1 Output | VOH | 1.6 | V | IOH = -0.4mA; VCC = 2.0V (Note 2) | 10 | ||
| Logic 1 Output | VOH | 2.4 | V | IOH = -1.0mA; VCC = 5V | 10 | ||
| Logic 0 Output | VOL | 0.4 | V | IOL = 1.5mA; VCC = 2.0V (Note 2) | 10 | ||
| Active Supply Current (Oscillator Enabled) | ICC1A | 0.4 | mA | VCC1 = 2.0V; CH = 0 (Notes 4, 11) | 10 | ||
| Active Supply Current (Oscillator Enabled) | ICC1A | 1.2 | mA | VCC1 = 5V; CH = 0 (Notes 4, 11) | 10 | ||
| Timekeeping Current (Oscillator Enabled) | ICC1T | 0.2 | 0.3 | A | VCC1 = 2.0V; CH = 0 (Notes 3, 11, 13) | 10 | |
| Timekeeping Current (Oscillator Enabled) | ICC1T | 0.45 | 1 | A | VCC1 = 5V; CH = 0 (Notes 3, 11, 13) | 10 | |
| Standby Current (Oscillator Disabled) | ICC1S | 1 | 100 | nA | VCC1 = 2.0V; CH = 1 (Notes 9, 11, 13) | 10 | |
| Active Supply Current (Oscillator Enabled) | ICC2A | 0.425 | mA | VCC2 = 2.0V; CH = 0 (Notes 4, 12) | 10 | ||
| Active Supply Current (Oscillator Enabled) | ICC2A | 1.28 | mA | VCC2 = 5V; CH = 0 (Notes 4, 12) | 10 | ||
| Timekeeping Current (Oscillator Enabled) | ICC2T | 25.3 | A | VCC2 = 2.0V; CH = 0 (Notes 3, 12) | 10 | ||
| Timekeeping Current (Oscillator Enabled) | ICC2T | 81 | A | VCC2 = 5V; CH = 0 (Notes 3, 12) | 10 | ||
| Standby Current (Oscillator Disabled) | ICC2S | 25 | A | VCC2 = 2.0V; CH = 1 (Notes 9, 12) | 10 | ||
| Standby Current (Oscillator Disabled) | ICC2S | 80 | A | VCC2 = 5V; CH = 1 (Notes 9, 12) | 10 | ||
| Input Capacitance | CI | 10 | pF | TA = +25°C | 11 | ||
| I/O Capacitance | CI/O | 15 | pF | TA = +25°C | 11 | ||
| Data to CLK Setup | tDC | 200 | ns | VCC = 2.0V (Note 6) | 11 | ||
| Data to CLK Setup | tDC | 50 | ns | VCC = 5V | 11 | ||
| CLK to Data Hold | tCDH | 280 | ns | VCC = 2.0V (Note 6) | 11 | ||
| CLK to Data Hold | tCDH | 70 | ns | VCC = 5V | 11 | ||
| CLK to Data Delay | tCDD | 800 | ns | VCC = 2.0V (Notes 6, 7, 8) | 11 | ||
| CLK to Data Delay | tCDD | 200 | ns | VCC = 5V (Notes 6, 7, 8) | 11 | ||
| CLK Low Time | tCL | 1000 | ns | VCC = 2.0V (Note 6) | 11 | ||
| CLK Low Time | tCL | 250 | ns | VCC = 5V | 11 | ||
| CLK High Time | tCH | 1000 | ns | VCC = 2.0V (Note 6) | 11 | ||
| CLK High Time | tCH | 250 | ns | VCC = 5V | 11 | ||
| CLK Frequency | tCLK | 0.5 | MHz | VCC = 2.0V (Note 6) | 11 | ||
| CLK Frequency | tCLK | 2 | MHz | VCC = 5V | 11 | ||
| CLK Rise and Fall | tR, tF | 2000 | ns | VCC = 2.0V | 11 | ||
| CLK Rise and Fall | tR, tF | 500 | ns | VCC = 5V | 11 | ||
| CE to CLK Setup | tCC | 4 | s | VCC = 2.0V (Note 6) | 11 | ||
| CE to CLK Setup | tCC | 1 | s | VCC = 5V | 11 | ||
| CLK to CE Hold | tCCH | 240 | ns | VCC = 2.0V (Note 6) | 11 | ||
| CLK to CE Hold | tCCH | 60 | ns | VCC = 5V | 11 | ||
| CE Inactive Time | tCWH | 4 | s | VCC = 2.0V (Note 6) | 11 | ||
| CE Inactive Time | tCWH | 1 | s | VCC = 5V | 11 | ||
| CE to I/O High Impedance | tCDZ | 280 | ns | VCC = 2.0V (Note 6) | 11 | ||
| CE to I/O High Impedance | tCDZ | 70 | ns | VCC = 5V | 11 | ||
| SCLK to I/O High Impedance | tCCZ | 280 | ns | VCC = 2.0V (Note 6) | 11 | ||
| SCLK to I/O High Impedance | tCCZ | 70 | ns | VCC = 5V | 11 | ||
| Voltage Range on Any Pin Relative to Ground | 7 | V | Relative to ground | 10 | |||
| Operating Temperature Range, Commercial | TA | 0 | 70 | °C | 10 | ||
| Storage Temperature Range | -55 | 125 | °C | 10 | |||
| Thermal Resistance, Junction-to-Ambient (8 SO, 150 mils) | THETA-JA | 170 | °C/W | 8 SO (150 mils) | 12 | ||
| Thermal Resistance, Junction-to-Case (8 SO, 150 mils) | THETA-JC | 40 | °C/W | 8 SO (150 mils) | 12 |
CAD (KiCad official)
- Symbol:
JHT1302ARZ - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
jht1302arz-etched.step/jht1302arz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);jht1302arz.step/jht1302arz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JYJE datasheet (13 pp, sha256
db0de3935c4f62f2, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).