AT7456E from ZHONGKEWEI, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	N.C.	unconnected	No connect. Internally floating; leave unconnected.
2	N.C.	unconnected	No connect. Internally floating; leave unconnected.
3	DVDD	power_in	Digital supply input, +3.15 V to +5.25 V (typ +5 V). Bypass with a 0.1 uF capacitor to DGND.
4	DGND	power_in	Digital ground return.
5	CLKIN	input	Crystal connection 1 / external clock input. Connect a 27 MHz parallel-resonant crystal between CLKIN and XFB, or drive CLKIN directly with a 27 MHz system reference clock (TTL/logic level).
6	XFB	output	Crystal feedback pin (connection 2). Connect a 27 MHz parallel-resonant crystal between CLKIN and XFB. If CLKIN is driven by an external 27 MHz clock, leave XFB floating.
7	CLKOUT	output	27 MHz system-clock buffered logic-level output; used to daisy-chain synchronous timing to additional devices.
8	CS	input	SPI chip-select, active-low. When CS is high, SDOUT is tri-stated (high impedance).
9	SDIN	input	SPI serial data input. Data is latched into the input register on the rising edge of SCLK.
10	SCLK	input	SPI serial clock input. Provides timing for SDIN capture and SDOUT update. Duty cycle must be between 40% and 60%; max clock ~10 MHz.
11	SDOUT	tri_state	SPI serial data output. Data is updated on the falling edge of SCLK. Enters high-impedance state when CS is high.
12	LOS	output	Loss-of-sync output, open-drain. Goes high when 32 consecutive line periods of sync are missing on VIN; goes low when 32 consecutive valid sync pulses are detected. Requires a 1 kohm pull-up to DVDD (or another compatible supply).
13	SYNC_IN	input	External composite-sync signal input. Used when VM0[7]=1 to feed an externally separated sync signal into the OSD timing generator.
14	N.C.	unconnected	No connect. Internally floating; leave unconnected.
15	N.C.	unconnected	No connect. Internally floating; leave unconnected.
16	N.C.	unconnected	No connect. Internally floating; leave unconnected.
17	VSYNC	output	Vertical-sync output, open-drain, active-low. Asserts low during the vertical-sync period of the video input. Can be recovered from VIN or generated internally in internal-sync mode. Requires a 1 kohm pull-up to DVDD or another compatible supply.
18	HSYNC	output	Horizontal-sync output, open-drain, active-low. Asserts low during the horizontal-sync period of the video input. Can be recovered from VIN or generated internally in internal-sync mode. Requires a 1 kohm pull-up to DVDD or another compatible supply.
19	RESET	input	System reset input, active-low. Minimum pulse width 1 us. 50 ms after RESET's rising edge, all SPI registers reset to defaults (no register access allowed during this time). 40 us after RESET's rising edge, all display memory cells reset to default value 00H.
20	AGND	power_in	Analog ground return.
21	AVDD	power_in	Analog supply input, +3.15 V to +5.25 V (typ +5 V). Bypass with a 0.1 uF capacitor to AGND.
22	VIN	input	PAL or NTSC CVBS composite-video input. Operating range 0.5 to 1.2 Vp-p (sync-detection range up to 2.0 Vp-p). Should be AC-coupled through 0.1 uF.
23	PGND	power_in	Driver (power) ground. Tie to AGND at a single point.
24	PVDD	power_in	Video-driver supply input, +3.15 V to +5.25 V (typ +5 V). Bypass with a 0.1 uF capacitor to PGND.
25	SAG	input	Sag (voltage-droop) correction input. Used with the output-coupling capacitor network to reduce line-time distortion at low frequencies. If sag correction is not used, connect SAG directly to VOUT.
26	VOUT	output	Composite video output. Drives up to two 150 ohm standard video loads; nominal 2 Vp-p swing (max 2.66 Vp-p), gain 2 V/V, bandwidth 6 MHz.
27	N.C.	unconnected	No connect. Internally floating; leave unconnected.
28	N.C.	unconnected	No connect. Internally floating; leave unconnected.
EP	EP	power_in	Exposed thermal pad on the HTSSOP-28 package. Internally connected to AGND. Solder to the AGND copper plane for improved thermal dissipation. Do not use EP as an electrical ground routing node.

Key specifications

Parameter	Value
Manufacturer	ZHONGKEWEI
Package	TSSOP-28-EP
Category	Memory
Pins	29

Ordering variants

AT7456E
AT7456ELAH

CAD (KiCad official)

Symbol: AT7456E
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: TSSOP-28-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`at7456e.step`	569 KB	You want the bare part, or you mark your own boards.
`at7456e-etched.step`	1.4 MB	You want the part with `AT7456E` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 405 faces against 183 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ZHONGKEWEI datasheet (38 pp, sha256 bc0500dff1b12afb, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF