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Contents

README

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BLUENRG-355AC

STMicroelectronics · RF Transceiver ICs · QFN-32-EP(5x5)

BLUENRG-355AC from STMicroelectronics, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB3 bidirectional I/O pin with 5 V tolerance; supports USART_CTS, LPUART_TX, TIM1_CH4 alternate functions; ADC_VINP0 analog input; wakeup capable.
2 PB2 bidirectional I/O pin with 5 V tolerance; supports USART_RTS_DE, PDM_DATA, TIM1_CH3 alternate functions; ADC_VINM0 analog input; wakeup capable.
3 PB1 bidirectional I/O pin with 5 V tolerance; supports SPI1_NSS, PDM_CLK, TIM1_ETR alternate functions; ADC_VINP1 analog input; wakeup capable.
4 PB0 bidirectional I/O pin with 5 V tolerance; supports USART_RX, LPUART_RTS_DE, TIM1_CH2N alternate functions; ADC_VINM1 analog input; wakeup capable.
5 PA11 bidirectional I/O pin with 5 V tolerance; supports MCO, SPI1_NSS, RX_SEQUENCE, SPI3_MOSI, TIM1_CH6, I2S3_SD alternate functions; provides GPIO output and RTC_OUT in DEEPSTOP mode; wakeup capable.
6 PA10 bidirectional I/O pin with 5 V tolerance; supports LCO, SPI1_MISO, TX_SEQUENCE, SPI3_MCK, TIM1_CH5, I2S3_MCK alternate functions; BOOT pin configuration; GPIO output in DEEPSTOP mode; wakeup capable.
7 PA9 bidirectional I/O pin with 5 V tolerance; supports USART_TX, SPI1_SCK, RTC_OUT, SPI3_NSS, TIM1_CH4, I2S3_WS alternate functions; GPIO output in DEEPSTOP mode; wakeup capable.
8 PA8 bidirectional I/O pin with 5 V tolerance; supports USART_RX, SPI1_MOSI, RX_SEQUENCE, SPI3_MISO, TIM1_CH3, I2S3_MISO alternate functions; GPIO output in DEEPSTOP mode; wakeup capable.
9 PA0 bidirectional I/O pin with 5 V tolerance and Fm+ capable; supports I2C1_SCL, USART_CTS, SPI2_MCK, TIM1_CH3, I2S2_MCK alternate functions; wakeup capable.
10 PA1 bidirectional I/O pin with 5 V tolerance and Fm+ capable; supports I2C1_SDA, SPI2_MISO, USART_TX, TIM1_CH4, I2S2_MISO alternate functions; wakeup capable.
11 PA2 bidirectional I/O pin with 5 V tolerance; supports SWDIO, USART_CK, TIM_BKIN, SPI3_MCK, TIM1_CH5, I2S3_MCK alternate functions; wakeup capable.
12 PA3 bidirectional I/O pin with 5 V tolerance; supports SWCLK, USART_RTS_DE, TIM_BKIN2, SPI3_SCK, TIM1_CH6, I2S3_SCK alternate functions; wakeup capable.
13 VDD2 power_in Battery voltage supply input, 1.7 to 3.6 V.
14 RF1 bidirectional RF input/output with 50 Ω characteristic impedance for antenna connection.
15 VDDRF power_in RF battery voltage supply input, 1.7 to 3.6 V.
16 OSCOUT bidirectional 32 MHz oscillator output for external crystal oscillator circuit.
17 OSCIN bidirectional 32 MHz oscillator input for external crystal oscillator circuit.
18 PB15 bidirectional I/O pin with 5 V tolerance; supports I2C1_SMBA, TX_SEQUENCE, MCO, TIM1_CH4N, TIM1_CH6, USART_TX alternate functions.
19 PB14 bidirectional I/O pin with 5 V tolerance and analog switch; supports SPI1_MOSI, I2C2_SDA, TIM1_ETR, TIM1_CH3N, TIM1_CH5, USART_RX alternate functions; VIN_PVD analog input.
20 PB13 bidirectional I/O pin with 5 V tolerance; supports SPI1_MISO, I2C2_SCL, PDM_CLK, TIM1_BKIN2, TIM1_CH4 alternate functions; SXTAL1 function for crystal oscillator.
21 PB12 bidirectional I/O pin with 5 V tolerance; supports SPI1_SCK, LCO, PDM_DATA, TIM1_BKIN, TIM1_CH3 alternate functions; SXTAL0 function for crystal oscillator.
22 VFBSD passive SMPS feedback voltage output for DC-DC converter step-down regulator.
23 VSS power_in Ground connection.
24 VLXSD passive SMPS inductor voltage input/output node.
25 VDDSD power_in Battery voltage supply input for SMPS, 1.7 to 3.6 V.
26 RSTN input Active-low reset input with internal pull-up resistor (25-55 kΩ) and 200 mV Schmitt trigger hysteresis.
27 VCAP passive Digital core voltage regulator output, nominally 1.2 V.
28 PB7 bidirectional I/O pin with 5 V tolerance and Fm+ capable; supports I2C2_SDA, SPI2_SCK, LPUART_RX, TIM1_CH2, I2S2_SCK alternate functions; wakeup capable.
29 PB6 bidirectional I/O pin with 5 V tolerance and Fm+ capable; supports I2C2_SCL, SPI2_NSS, LPUART_TX, TIM1_CH1, I2S2_WS alternate functions; wakeup capable.
30 PB5 bidirectional I/O pin with 3.6 V tolerance; supports LPUART_RX, SPI2_MOSI, PDM_CLK, I2S2_SD alternate functions; PGA_VBIAS_MIC analog output; wakeup capable.
31 PB4 bidirectional I/O pin with 5 V tolerance; supports LPUART_TX, SPI2_MISO, PDM_DATA, I2S2_MISO alternate functions; PGA_VIN analog input; wakeup capable.
32 VDD1 power_in Battery voltage supply input, 1.7 to 3.6 V.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package QFN-32-EP(5x5)
Category RF And Wireless
Pins 33

CAD (KiCad official)

  • Symbol: BLUENRG-355AC
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: bluenrg-355ac-etched.step / bluenrg-355ac-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bluenrg-355ac.step / bluenrg-355ac.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (73 pp, sha256 c3c8def9f2699f65, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF