ADAU1401AWBSTZ from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AGND	power_in	Analog ground; AGND, DGND, and PGND can be tied together in a common ground plane and AGND should be decoupled to an AVDD pin with a 100 nF capacitor.
2	ADC0	passive	Analog audio input 0 takes a 100 μA rms full-scale current input, and an 18 kΩ resistor gives a 2 V rms full-scale input.
3	ADC_RES	passive	ADC reference current pin whose full-scale current is set by an external 18 kΩ resistor connected to ground.
4	ADC1	passive	Analog audio input 1 takes a 100 μA rms full-scale current input, and an 18 kΩ resistor gives a 2 V rms full-scale input.
5	RESET	input	Active-low reset input that triggers reset on a high-to-low edge and exits reset on a low-to-high edge.
6	SELFBOOT	input	Selects control port mode when low or self-boot when high, with self-boot initiated when the device leaves reset.
7	ADDR0	input	I2C and SPI address bit 0 which, combined with ADDR1, allows up to four devices on one I2C bus.
8	MP4/INPUT_LRCLK	bidirectional	Multipurpose GPIO or serial input port LRCLK that clocks the SDATA_IN inputs and functions as slave only.
9	MP5/INPUT_BCLK	bidirectional	Multipurpose GPIO or serial input port BCLK that clocks the SDATA_IN inputs and functions as slave only.
10	MP1/SDATA_IN1	bidirectional	Multipurpose GPIO or serial input port data 1.
11	MP0/SDATA_IN0	bidirectional	Multipurpose GPIO or serial input port data 0, which also carries the TDM input data.
12	DGND	power_in	Digital ground that should be decoupled to a DVDD pin with a 100 nF capacitor.
13	DVDD	power_in	1.8 V digital supply that can be supplied externally or generated by the on-board regulator and should be decoupled to DGND with 100 nF.
14	MP7/SDATA_OUT1	bidirectional	Multipurpose GPIO or serial output port data 1.
15	MP6/SDATA_OUT0/TDM_IN	bidirectional	Multipurpose GPIO or serial output port data 0, which also serves as the TDM data input.
16	MP10/OUTPUT_LRCLK	bidirectional	Multipurpose GPIO or serial output port LRCLK that can operate as master or slave.
17	VDRIVE	output	Drives the base of the external PNP transistor of the 1.8 V regulator and can be tied to ground if the regulator is unused.
18	IOVDD	power_in	Supply for input and output pins that sets the highest digital input voltage and should always be set to 3.3 V.
19	MP11	bidirectional	Multipurpose GPIO or serial output port BCLK, which can also provide a divided master clock.
20	ADDR1/CDATA/WB	input	I2C address bit 1, SPI data input, and EEPROM writeback trigger that acts on a rising edge by default.
21	CLATCH/WP	bidirectional	SPI latch signal, or self-boot EEPROM write protect as an open-collector output that should be pulled high to 3.3 V.
22	SDA/COUT	bidirectional	I2C open-collector data line or SPI data output, and the I2C line requires a 2.2 kΩ pull-up resistor.
23	SCL/CCLK	bidirectional	I2C open-collector clock or SPI clock, and the line requires a 2.2 kΩ pull-up resistor with voltage not exceeding IOVDD (3.3 V).
24	DVDD	power_in	1.8 V digital supply that should be decoupled to DGND with a 100 nF capacitor.
25	DGND	power_in	Digital ground that should be decoupled to a DVDD pin with a 100 nF capacitor.
26	MP9/SDATA_OUT3/AUX_ADC0	bidirectional	Multipurpose GPIO, serial output port data 3, or auxiliary ADC input 0 with 3.0 V full-scale input.
27	MP8/SDATA_OUT2/AUX_ADC3	bidirectional	Multipurpose GPIO, serial output port data 2, or auxiliary ADC input 3 with 3.0 V full-scale input.
28	MP3/SDATA_IN3/AUX_ADC2	bidirectional	Multipurpose GPIO, serial input port data 3, or auxiliary ADC input 2 with 3.0 V full-scale input.
29	MP2/SDATA_IN2/AUX_ADC1	bidirectional	Multipurpose GPIO, serial input port data 2, or auxiliary ADC input 1 with 3.0 V full-scale input.
30	RSVD	passive	Reserved pin that must be tied to ground directly or through a pull-down resistor.
31	OSCO	output	Crystal oscillator output that requires a 100 Ω damping resistor to the crystal and should not directly drive another IC.
32	MCLKI	input	Master clock input that accepts a 3.3 V clock signal or the crystal oscillator circuit output.
33	PGND	power_in	PLL ground that should be decoupled to PVDD with a 100 nF capacitor.
34	PVDD	power_in	3.3 V supply for the PLL and auxiliary ADC analog section that should be decoupled to PGND with a 100 nF capacitor.
35	PLL_LF	passive	PLL loop filter connection that requires two capacitors and a resistor as shown in Figure 15.
36	AVDD	power_in	3.3 V analog supply that should be decoupled to AGND with a 100 nF capacitor.
37	AGND	power_in	Analog ground that should be decoupled to an AVDD pin with a 100 nF capacitor.
38	PLL_MODE0	input	PLL mode setting bit 0 that sets the master clock PLL input frequency and should only be changed while RESET is held low.
39	PLL_MODE1	input	PLL mode setting bit 1 that sets the master clock PLL input frequency and should only be changed while RESET is held low.
40	CM	output	1.5 V common-mode reference that requires a 47 μF decoupling capacitor to ground and should not source current when used as a bias.
41	FILTD	output	DAC filter decoupling pin at 1.5 V that requires a 10 μF capacitor to ground.
42	AGND	power_in	Analog ground that should be decoupled to an AVDD pin with a 100 nF capacitor.
43	VOUT3	output	DAC3 output with a full-scale output voltage of 0.9 V rms.
44	VOUT2	output	DAC2 output with a full-scale output voltage of 0.9 V rms.
45	VOUT1	output	DAC1 output with a full-scale output voltage of 0.9 V rms.
46	VOUT0	output	DAC0 output with a full-scale output voltage of 0.9 V rms.
47	FILTA	output	ADC filter decoupling pin at 1.5 V that requires a 10 μF capacitor to ground.
48	AVDD	power_in	3.3 V analog supply that should be decoupled to AGND with a 100 nF capacitor.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Voltage, High	VIH	2			V		5
Input Voltage, Low	VIL			0.8	V		5
Output Voltage, High	VOH	2			V	IOH = 2 mA	5
Output Voltage, Low	VOL			0.8	V	IOL = 2 mA	5
Input Leakage, High	IIH			1	μA	Excluding MCLKI	5
Input Leakage, Low	IIL			1	μA	Excluding MCLKI and bidirectional pins	5
Bidirectional Pin Pull-Up Current, Low				150	μA		5
MCLKI Input Leakage, High	IIH			3	μA	MCLKI	5
MCLKI Input Leakage, Low	IIL			3	μA	MCLKI	5
GPIO Output Drive				2	mA		5
Gain Error (ADC)		-11		11	%		5
Interchannel Gain Mismatch (ADC)			25	250	mdB		5
DC Bias (ADC)		1.4	1.5	1.6	V		5
Gain Error (DAC)		-10		10	%		5
Interchannel Gain Mismatch (DAC)			25	250	mdB		5
DC Bias (DAC)		1.4	1.5	1.6	V		5
Absolute Voltage, CM Pin		1.4	1.5	1.6	V		5
Full-Scale Analog Input (Auxiliary ADC)		2.8	2.95	3.1	V		5
Input Impedance (Auxiliary ADC)		17.8	30	42	kΩ		5
Analog Current (AVDD and PVDD)			50	85	mA		6
Digital Current (DVDD)			25	40	mA		6
Analog Current, Reset			35	55	mA		6
Digital Current, Reset			1.5	4.5	mA		6
Power Supply Rejection Ratio	PSRR			50	dB	1 kHz, 200 mV p-p Signal at AVDD	6
Functionality Guaranteed (ambient temperature)		-40		105	°C	ambient	6
DVDD Voltage (regulator output)	DVDD	1.7	1.8	1.84	V		6
MCLKI period, 512 × fS mode	tMP	36		244	ns	MCLKI period, 512 × fS mode.	7
MCLKI period, 384 × fS mode	tMP	48		366	ns	MCLKI period, 384 × fS mode.	7
MCLKI period, 256 × fS mode	tMP	73		488	ns	MCLKI period, 256 × fS mode.	7
MCLKI period, 64 × fS mode	tMP	291		1953	ns	MCLKI period, 64 × fS mode.	7
INPUT_BCLK low pulse width	tBIL	40			ns	INPUT_BCLK low pulse width.	7
INPUT_BCLK high pulse width	tBIH	40			ns	INPUT_BCLK high pulse width.	7
INPUT_LRCLK setup	tLIS	10			ns	time to INPUT_BCLK rising.	7
INPUT_LRCLK hold	tLIH	10			ns	time from INPUT_BCLK rising.	7
SDATA_INx setup	tSIS	10			ns	time to INPUT_BCLK rising.	7
SDATA_INx hold	tSIH	10			ns	time from INPUT_BCLK rising.	7
OUTPUT_LRCLK setup in slave mode	tLOS	10			ns	slave mode.	7
OUTPUT_LRCLK hold in slave mode	tLOH	10			ns	slave mode.	7
OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew	tTS	5			ns		7
SDATA_OUTx delay in slave mode	tSODS	40			ns	slave mode; time from OUTPUT_BCLK falling.	7
SDATA_OUTx delay in master mode	tSODM	40			ns	master mode; time from OUTPUT_BCLK falling.	7
Digital supply voltage DVDD to Ground	DVDD	0		2.2	V		10
Analog supply voltage AVDD to Ground	AVDD	0		4	V		10
IOVDD to Ground	IOVDD	0		4	V		10
Digital Inputs voltage		-0.3			V	upper limit printed as IOVDD + 0.3 V	10
Maximum Junction Temperature				135	°C		10
Storage Temperature Range		-65		150	°C		10
Soldering				300	°C	10 sec	10
Thermal resistance junction to ambient, 48-Lead LQFP	θJA		72		°C/W	worst-case, device soldered in circuit board for surface-mount packages	10
Thermal resistance junction to case, 48-Lead LQFP	θJC		19.5		°C/W		10

CAD (KiCad official)

Symbol: ADAU1401AWBSTZ
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: adau1401awbstz-etched.step / adau1401awbstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adau1401awbstz.step / adau1401awbstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (52 pp, sha256 2a7bfd67c77449c4, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADAU1401AWBSTZ

Verified ADAU1401AWBSTZ

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3D Model

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Schematic Symbol

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Datasheet

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