component
AD5060BRJZ-1REEL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), SOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5060BRJZ-1REEL7
Analog Devices · Digital To Analog Converters (DACs) · SOT-23-8
AD5060BRJZ-1REEL7 from Analog Devices, in a SOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIN | input | Serial data input clocked into the 24-bit shift register on the falling edge of SCLK. |
| 2 | VDD | power_in | Power supply input operated from 2.7 V to 5.5 V and should be decoupled to GND. |
| 3 | VREF | power_in | Reference voltage input, with an input range of 2 V to VDD − 50 mV. |
| 4 | VOUT | output | Analog output voltage from the DAC, with an output range of 0 V to VREF. |
| 5 | AGND | power_in | Ground reference point for the analog circuitry. |
| 6 | DACGND | power_in | Ground input to the DAC core. |
| 7 | SYNC | input | Active-low level-triggered frame synchronization input, where a rising edge before the 24th clock acts as an interrupt that ignores the write. |
| 8 | SCLK | input | Serial clock input for clocking data into the input shift register at rates up to 30 MHz. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOT-23-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), B grade | INL | -1 | 0.5 | 1 | LSB | -40 C to +85 C, AD5040/AD5060 B grade | 3 |
| Differential Nonlinearity (DNL) | DNL | -1 | 0.5 | 1 | LSB | Guaranteed monotonic, -40 C to +85 C, AD5040/AD5060 | 3 |
| Total Unadjusted Error (TUE) | TUE | -2 | 0.1 | 2 | mV | -40 C to +85 C, AD5040/AD5060 | 3 |
| Gain Error | -0.02 | 0.01 | 0.02 | % of FSR | TA = -40 C to +85 C, AD5040/AD5060 | 3 | |
| Offset Error | -1.5 | 0.02 | 1.5 | mV | TA = -40 C to +85 C, AD5040/AD5060 | 3 | |
| Full-Scale Error | -2 | 0.05 | 2 | mV | All 1s loaded to DAC register, TA = -40 C to +85 C, AD5060 | 3 | |
| Output Voltage Range | VOUT | 0 | V | Maximum is VREF | 3 | ||
| VREF Input Range | VREF | 2 | V | Maximum is VDD - 50 mV | 4 | ||
| Input Current | IIN | -2 | 1 | 2 | μA | Total current flowing into all pins | 4 |
| VIL, Input Low Voltage | VIL | 0.8 | V | VDD = 4.5 V to 5.5 V | 4 | ||
| VIH, Input High Voltage | VIH | 2 | V | VDD = 2.7 V to 5.5 V | 4 | ||
| VIH, Input High Voltage | VIH | 1.8 | V | VDD = 2.7 V to 3.6 V | 4 | ||
| Supply Voltage | VDD | 2.7 | 5.5 | V | All digital inputs at 0 V or VDD | 4 | |
| Normal Mode Supply Current (IDD) | IDD | 1 | 1.2 | mA | VIN = VDD and VIL = GND, VDD = 5.0 V, VREF = 4.096 V, code = midscale | 4 | |
| Power-Down Mode Supply Current (IDD) | IDD | 0.33 | 1 | μA | VIH = VDD and VIL = GND, VDD = 5.5 V, VREF = 4.096 V, code = midscale | 4 | |
| Minimum SCLK Cycle Time | t1 | 33 | ns | SCLK cycle time | 5 | ||
| Minimum SCLK High Time | t2 | 5 | ns | SCLK high time | 5 | ||
| Minimum SCLK Low Time | t3 | 3 | ns | SCLK low time | 5 | ||
| SYNC to SCLK Falling Edge Setup Time | t4 | 10 | ns | SYNC to SCLK falling edge setup time | 5 | ||
| Data Setup Time | t5 | 3 | ns | Data setup time | 5 | ||
| Data Hold Time | t6 | 2 | ns | Data hold time | 5 | ||
| SCLK Falling Edge to SYNC Rising Edge | t7 | 0 | ns | SCLK falling edge to SYNC rising edge | 5 | ||
| Minimum SYNC High Time | t8 | 12 | ns | Minimum SYNC high time | 5 | ||
| SYNC Rising Edge to Next SCLK Fall Ignore | t9 | 9 | ns | SYNC rising edge to next SCLK fall ignore | 5 | ||
| Maximum SCLK Frequency | 30 | MHz | Maximum SCLK frequency | 5 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| Digital Input Voltage to GND | -0.3 | V | Maximum is VDD + 0.3 V | 6 | |||
| VOUT to GND | VOUT | -0.3 | V | Maximum is VDD + 0.3 V | 6 | ||
| VREF to GND | VREF | -0.3 | V | Maximum is VDD + 0.3 V | 6 | ||
| Operating Temperature Range | TA | -40 | 85 | °C | Industrial (A, B Grade) | 6 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 6 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 6 | |||
| Reflow Soldering Peak Temperature | 260 | °C | Pb-free reflow soldering | 6 | |||
| Time-at-Peak Temperature | 10 | 40 | sec | Pb-free reflow soldering | 6 | ||
| Thermal Impedance Junction-to-Ambient | θJA | 206 | °C/W | SOT-23 package | 6 | ||
| Thermal Impedance Junction-to-Case | θJC | 91 | °C/W | SOT-23 package | 6 |
CAD (KiCad official)
- Symbol:
AD5060BRJZ-1REEL7 - Footprint:
Package_TO_SOT_SMD:SOT-23-8 - 3D model: SOT-23-8 (KiCad packages3D, STEP)
- 3D model files:
ad5060brjz-1reel7-etched.step/ad5060brjz-1reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5060brjz-1reel7.step/ad5060brjz-1reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
79ef63bfa75dcc21, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).