SN65HVD55DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	No internal connection.
2	R	output	Receiver output, driven according to the bus inputs A and B when the receiver is enabled (RE low), with 8 mA maximum high/low output current.
3	RE	input	Active-low receiver enable; with DE low and RE high for 300 ns or more the device enters low-power standby mode.
4	DE	input	Active-high driver enable; with DE low and RE high for 300 ns or more the device enters low-power standby mode.
5	D	input	Driver data input; if left open when the driver is enabled, the driver outputs default to A high and B low.
6	GND	power_in	Ground connection (network ground reference for all voltages except differential bus voltages).
7	GND	power_in	Ground connection (network ground reference for all voltages except differential bus voltages).
8	NC	unconnected	No internal connection.
9	Y	tri_state	Non-inverting 3-state driver output on the bus, rated for -7 V to 12 V common-mode and up to 60 mA output current.
10	Z	tri_state	Inverting 3-state driver output on the bus, rated for -7 V to 12 V common-mode and up to 60 mA output current.
11	B	input	Inverting differential receiver input, operating over -7 V to 12 V with differential input up to ±12 V.
12	A	input	Non-inverting differential receiver input, operating over -7 V to 12 V with differential input up to ±12 V.
13	VCC	power_in	Supply voltage, 4.5 V to 5.5 V recommended (absolute maximum 6 V).
14	VCC	power_in	Supply voltage, 4.5 V to 5.5 V recommended (absolute maximum 6 V).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-14
Category	Communication Interface Chip/UART/485/232
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	4.5		5.5	V		6
Voltage at any bus terminal (separately or common mode)	VI or VIC	-7		12	V		6
Signaling rate (SN65HVD52, SN65HVD55 grade)	1/tUI			1	Mbps	SN65HVD52, SN65HVD55	6
Differential load resistance	RL	54	60		Ω		6
High-level input voltage D, DE, RE	VIH	2			V	Maximum is VCC	6
Low-level input voltage D, DE, RE	VIL	0		0.8	V		6
Differential input voltage	VID	-12		12	V		6
High-level output current, driver	IOH	-60			mA	Driver	6
High-level output current, receiver	IOH	-8			mA	Receiver	6
Low-level output current, driver	IOL			60	mA	Driver	6
Low-level output current, receiver	IOL			8	mA	Receiver	6
Junction temperature	TJ	-40		150	°C		6
Supply voltage range	VCC	-0.3		6	V		6
Voltage range at any bus terminal (A, B, Y, Z)	V(A), V(B), V(Y), V(Z)	-9		14	V		6
Voltage input, transient pulse (A, B, Y, Z)	V(TRANS)	-50		50	V	Through 100 Ω, see Figure 8-12	6
Voltage input range (D, DE, RE)	VI	-0.5		7	V		6
Output current (receiver output only)	IO			11	mA	Receiver output only	6
Input clamp voltage	VI(K)			-1.5	V	II = -18 mA	7
Steady-state differential output voltage, no load	/VOD(SS)/	4			V	IO = 0; maximum is VCC	7
Steady-state differential output voltage (RS-485)	/VOD(SS)/	1.7	2.6		V	RL = 54 Ω, See Figure 8-1 (RS-485)	7
Steady-state differential output voltage (RS-422)	/VOD(SS)/	2.4	3.2		V	RL = 100 Ω, See Figure 8-1 (RS-422)	7
Differential output voltage overshoot and undershoot	VOD(RING)			10	%	RL = 54 Ω, CL = 50 pF, See Figure 8-5	7
Peak-to-peak common-mode output voltage (HVD52, HVD55)	VOC(PP)	0.4			V	See Figure 8-4	7
Steady-state common-mode output voltage	VOC(SS)	2.2		3.3	V	See Figure 8-4	7
High-impedance state output current (HVD53, HVD54, HVD55)	IZ(Z) or IY(Z)			90	μA	VCC = 5 V or 0 V, DE = 0 V, VZ or VY = 12 V, other input at 0 V	7
High-impedance state output current (HVD53, HVD54, HVD55)	IZ(Z) or IY(Z)	-10			μA	VCC = 5 V or 0 V, DE = 0 V, VZ or VY = -7 V, other input at 0 V	7
Short-circuit output current	IZ(S) or IY(S)	-250		250	mA	VZ or VY = -7 V, other input at 0 V	7
Input current (D, DE)	II	0		100	μA		7
Propagation delay time, low-to-high-level output (HVD52, HVD55)	tPLH	90	143	230	ns	RL = 54 Ω, CL = 50 pF, See Figure 8-5	8
Propagation delay time, high-to-low-level output (HVD52, HVD55)	tPHL	90	143	230	ns	RL = 54 Ω, CL = 50 pF, See Figure 8-5	8
Differential output signal rise time (HVD52, HVD55)	tr	120	197	300	ns	RL = 54 Ω, CL = 50 pF, See Figure 8-5	8
Differential output signal fall time (HVD52, HVD55)	tf	120	192	300	ns	RL = 54 Ω, CL = 50 pF, See Figure 8-5	8
Propagation delay time, high-impedance-to-high-level output (HVD55)	tPZH1			380	ns	RL = 110 Ω, RE at 0 V, See Figure 8-6; D = 3 V and S1 = Y, D = 0 V and S1 = Z	8
Propagation delay time, high-level-to-high-impedance output (HVD55)	tPHZ			110	ns		8
Propagation delay time, high-impedance-to-low-level output (HVD55)	tPZL1			420	ns	RL = 110 Ω, RE at 0 V, See Figure 8-7; D = 3 V and S1 = Z, D = 0 V and S1 = Y	8
Propagation delay time, low-level-to-high-impedance output (HVD55)	tPLZ			160	ns		8
Propagation delay time, standby-to-high-level output	tPZH2			3300	ns	RL = 110 Ω, RE at 3 V, See Figure 8-6; D = 3 V and S1 = Y, D = 0 V and S1 = Z	8
Propagation delay time, standby-to-low-level output	tPZL2			3300	ns	RL = 110 Ω, RE at 3 V, See Figure 8-7; D = 3 V and S1 = Z, D = 0 V and S1 = Y	8
Positive-going differential input threshold voltage	VIT+			-0.02	V	IO = -8 mA	9
Negative-going differential input threshold voltage	VIT-	-0.2			V	IO = 8 mA	9
Output voltage	VO	4			V	VID = 200 mV, IO = -8 mA, See Figure 8-8	9
Output voltage	VO			0.3	V	VID = -200 mV, IO = 8 mA, See Figure 8-8	9
Bus input current (HVD55)	IA or IB		0.05	0.1	mA	VA or VB = 12 V, other input at 0 V	9
Bus input current (HVD55)	IA or IB	-0.1		-0.05	mA	VA or VB = -7 V	9
Propagation delay time, low-to-high-level output (HVD55)	tPLH		43	55	ns	VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 8-9	10
Propagation delay time, high-to-low-level output (HVD55)	tPHL		47	60	ns	VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 8-9	10
Output signal rise time	tr		2.3	4	ns		10
Output enable time to high level	tPZH1			10	ns		10
Output enable time to low level	tPZL1			10	ns		10
Supply current (receiver enabled, driver disabled, HVD54/HVD55)	ICC			2.9	mA	RE at 0 V, D at 0 V or VCC, DE at 0 V, No load (Receiver enabled and driver disabled)	9
Supply current (receiver and driver disabled, standby)	ICC		0.08	1	μA	RE at VCC, D at VCC, DE at 0 V, No load (Receiver disabled and driver disabled)	9
Supply current (receiver and driver enabled, HVD54/HVD55)	ICC			8	mA	RE at 0 V, D at 0 V or VCC, DE at VCC, No load (Receiver enabled and driver enabled)	9
Supply current (receiver disabled, driver enabled, HVD54/HVD55)	ICC			7.7	mA	RE at VCC, D at 0 V or VCC, DE at VCC, No load (Receiver disabled and driver enabled)	9
Junction-to-ambient thermal resistance (high-K board)	θJA		93.2		°C/W	High-K board	11
Junction-to-board thermal resistance (high-K board)	θJB		49.4		°C/W	High-K board	11
Junction-to-case thermal resistance (no board)	θJC		47.5		°C/W	No board	11
Device power dissipation (HVD55, 1 Mbps)	PD		383		mW	RL= 60Ω, CL = 50 pF, DE at VCC, RE at 0 V, input to D a 50% duty cycle square wave at 1 Mbps	11
Ambient air temperature (low-K board, no airflow)	TA	-40		85	°C	Low-K board, no airflow	11
Ambient air temperature (high-K board, no airflow)	TA	-40		85	°C	High-K board, no airflow	11

CAD (KiCad official)

Symbol: SN65HVD55DR
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: sn65hvd55dr-etched.step / sn65hvd55dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd55dr.step / sn65hvd55dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 f0a968fd6764b7d7, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN65HVD55DR

Verified SN65HVD55DR

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3D Model

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