GN4051B from GN Semic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Y4	bidirectional	Independent analog I/O channel 4. Connects to common Z when address = 100 and E is low. Analog signal range: VEE to VDD.
2	Y6	bidirectional	Independent analog I/O channel 6. Connects to common Z when address = 110 and E is low.
3	Z	bidirectional	Common analog I/O. Bidirectional: signals may flow Z→Yn (demux) or Yn→Z (mux). Routed to one of Y0-Y7 selected by A2:A0 when E is low.
4	Y7	bidirectional	Independent analog I/O channel 7. Connects to common Z when address = 111 and E is low.
5	Y5	bidirectional	Independent analog I/O channel 5. Connects to common Z when address = 101 and E is low.
6	E	input	Active-low enable input. When E = low, the selected Yn↔Z channel is on. When E = high, all channels are OFF (high-impedance) regardless of A2:A0. Digital logic input referenced to VSS.
7	VEE	power_in	Negative analog supply (typically 0 V to −6 V). Sets the negative excursion limit for analog signals through the switch. Tie to VSS (0 V) for single-supply digital-signal switching; connect to a negative rail for bipolar analog signals. VDD−VEE must not exceed 9 V.
8	VSS	power_in	Digital ground / logic reference (0 V). Reference for A0-A2 and E logic thresholds.
9	A2	input	Address select input, MSB of the 3-bit channel select. Combined with A1:A0 to choose which Y0-Y7 connects to Z. Logic input referenced to VSS/VDD; VIH ≥ 3.5 V at VDD = 5 V.
10	A1	input	Address select input, middle bit of the 3-bit channel select.
11	A0	input	Address select input, LSB of the 3-bit channel select.
12	Y3	bidirectional	Independent analog I/O channel 3. Connects to common Z when address = 011 and E is low.
13	Y0	bidirectional	Independent analog I/O channel 0. Connects to common Z when address = 000 and E is low.
14	Y1	bidirectional	Independent analog I/O channel 1. Connects to common Z when address = 001 and E is low.
15	Y2	bidirectional	Independent analog I/O channel 2. Connects to common Z when address = 010 and E is low.
16	VDD	power_in	Positive supply, 3.0 V to 9.0 V (absolute max 12 V). Sets the positive rail for both the digital logic and the analog switch channels. Decouple to VSS with 100 nF close to the pin.

Key specifications

Parameter	Value
Manufacturer	GN Semic
Package	SOP-16
Category	Interface
Pins	16

CAD (KiCad official)

Symbol: GN4051B
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`gn4051b.step`	217 KB	You want the bare part, or you mark your own boards.
`gn4051b-etched.step`	2.0 MB	You want the part with `GN4051B` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 519 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: GN Semic datasheet (15 pp, sha256 1357b3d1e1e4fd1c, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF