component
BQ296113DSGR
Public Made by Adomby adom
Texas Instruments Battery Management, WSON-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownBQ296113DSGR
Texas Instruments · Battery Management · WSON-8-EP(2x2)
BQ296113DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input; the datasheet gives a recommended VDD range of 3 V to 20 V and an absolute maximum of 30 V with respect to VSS. |
| 2 | V4 | input | Sense input for the positive voltage of the fourth cell from the bottom of the stack. |
| 3 | V3 | input | Sense input for the positive voltage of the third cell from the bottom of the stack. |
| 4 | V2 | input | Sense input for the positive voltage of the second cell from the bottom of the stack. |
| 5 | V1 | input | Sense input for the positive voltage of the lowest cell from the bottom of the stack, with cell input range 0 V to 5 V per the recommended conditions. |
| 6 | VSS | power_in | Electrically connected to integrated circuit ground and the negative terminal of the lowest cell in the stack. |
| 7 | REG | output | Regulated supply output that requires an external ceramic capacitor for stability; absolute maximum REG to VSS is 3.6 V. |
| 8 | OUT | output | Analog output drive for an overvoltage fault signal, CMOS output high or open-drain active low; absolute maximum OUT to VSS is 30 V. |
| 9 | PWPD | power_in | Exposed pad; TI recommends connecting it to VSS on the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-8-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VDD | VDD | 3 | 20 | V | 5 | ||
| Supply voltage, VDD with REG output on | VDD | 4 | V | REG output on | 5 | ||
| Input voltage range | Vn - Vn-1, V1 - VSS | 0 | 5 | V | Vn - Vn-1, V1 - VSS | 5 | |
| Operating ambient temperature range | TA | -40 | 110 | °C | 5 | ||
| Supply voltage absolute maximum | VDD - VSS | -0.3 | 30 | V | 5 | ||
| Input voltage absolute maximum | V4 - V3, V3 - V2, V2 - V1, V1 - VSS | -0.3 | 30 | V | 5 | ||
| REG input voltage absolute maximum | REG - VSS | -0.3 | 3.6 | V | 5 | ||
| Output voltage absolute maximum | OUT - VSS | -0.3 | 30 | V | 5 | ||
| Lead temperature | TSOLDER | 300 | °C | soldering, 10 s | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Overvoltage detection hysteresis | VHYS | 250 | 300 | 400 | mV | 6 | |
| OV detection accuracy | VOA | -10 | 10 | mV | TA = 25°C | 6 | |
| OV detection accuracy across temperature | VOADRIFT | -40 | 40 | mV | TA = -40°C | 6 | |
| OV detection accuracy across temperature | VOADRIFT | -20 | 20 | mV | TA = 0°C | 6 | |
| OV detection accuracy across temperature | VOADRIFT | -24 | 24 | mV | TA = 60°C | 6 | |
| OV detection accuracy across temperature | VOADRIFT | -54 | 54 | mV | TA = 110°C | 6 | |
| Supply current with REG on | IDD | 4 | 6 | µA | (Vn - Vn-1) = 2V to 4.15V, n = 1 to 4, VDD = top Vn voltage, (V1 - VSS) > VUVREG, IREG = 0mA, TA = 0°C to 60°C | 6 | |
| Supply current with REG on | IDD | 8 | µA | (Vn - Vn-1) = 2V to 4.15V, n = 1 to 4, VDD = top Vn voltage, (V1 - VSS) > VUVREG, IREG = 0mA, TA = -40°C to 110°C | 6 | ||
| Supply current with REG off | IDD | 1 | 2 | µA | (Vn - Vn-1) = 2V to 4.15V, n = 1 to 4, VDD = top Vn voltage, (V1 - VSS) < VUVREG, TA = 0°C to 60°C | 6 | |
| Supply current with REG off | IDD | 4 | µA | (Vn - Vn-1) = 2V to 4.15V, n = 1 to 4, VDD = top Vn voltage, (V1 - VSS) < VUVREG, TA = -40°C to 110°C | 6 | ||
| Input current at Vx pins | IIN | -0.1 | 0.1 | µA | (Vn - Vn-1) = (V1 - VSS) = 3.8V, VDD = top Vn voltage, TA = 25°C | 6 | |
| Output drive voltage, active high | VOUT | 6 | 7 | 8 | V | (Vn - Vn-1) or (V1 - VSS) > VOV, IOH = 100µA, VDD = top Vn voltage | 6 |
| Output low voltage (no OV) | VOL | 250 | 400 | mV | (Vn - Vn-1) and (V1 - VSS) < VOV, VDD = sum of the cell stack voltage, IOL = 100µA measured into OUT pin | 6 | |
| OUT source current (during OV) | IOUTH | 4.5 | mA | (Vn - Vn-1), (V3 - V2), or (V1 - VSS) > VOV, VDD = top Vn voltage, forced OUT = 0V, measured out of OUT pin | 6 | ||
| OUT sink current (no OV) | IOUTL | 0.5 | 14 | mA | (Vn - Vn-1) and (V1 - VSS) < VOV, VDD = top Vn voltage, forced OUT = VDD, measured into OUT pin, pull-up RPU = 5kΩ to VDD | 6 | |
| OV delay time, 3-s delay option | tDELAY | 2.4 | 3 | 3.6 | s | Internal fixed delay, 3-s delay option | 6 |
| OV delay timer count reset time | tDELAY_RESET | 0.6 | ms | Internal fixed delay; tDELAY resets when the cell voltage falls below VOV for tDELAY_RESET | 6 | ||
| REG supply at 500µA load, 3.3V | VREG | 3.234 | 3.3 | 3.366 | V | VDD ≥ 4V, IREG = 500µA, CREG = 0.47µF, VREG = 3.3V | 7 |
| REG supply from 0 to 2mA load, 3.3V | VREG | 3.2 | 3.3 | 3.4 | V | VDD ≥ 4V, IREG = 0µA to 2mA, CREG = 0.47µF, VREG = 3.3V | 7 |
| REG current output | IREG | 0 | 2 | mA | VDD ≥ 4V, CREG = 0.47µF | 7 | |
| REG pull-down resistor | RREG_PD | 20 | 30 | 45 | kΩ | REG is disabled | 7 |
| Undervoltage detection accuracy | VUVREG | -50 | 50 | mV | Factory configuration: 2.0V to 3.5V in 50mV steps, TA = 25°C | 7 | |
| Undervoltage detection hysteresis | VUVHYS | 250 | 300 | 400 | mV | 7 | |
| Undervoltage detection delay | tUVDELAY | 4.5 | 6 | 7.5 | s | 7 | |
| Junction-to-ambient thermal resistance | RθJA | 62 | °C/W | DSG (WSON) 8 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 72 | °C/W | DSG (WSON) 8 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 32.5 | °C/W | DSG (WSON) 8 pins | 5 | ||
| Junction-to-top characterization parameter | ψJT | 1.6 | °C/W | DSG (WSON) 8 pins | 5 | ||
| Junction-to-board characterization parameter | ψJB | 33 | °C/W | DSG (WSON) 8 pins | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 10 | °C/W | DSG (WSON) 8 pins | 5 |
CAD (KiCad official)
- Symbol:
BQ296113DSGR - Footprint:
Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm - 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
bq296113dsgr-etched.step/bq296113dsgr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq296113dsgr.step/bq296113dsgr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
63e2aa2b5e24079f, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).