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MC74HC393ADTR2G

Public Made by Adom

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onsemi Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MC74HC393ADTR2G

onsemi · Logic ICs · TSSOP-14

MC74HC393ADTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK a input Clock input for counter A; the internal flip-flops toggle and the count advances on high-to-low transitions of this input.
2 RESET a input Active-high asynchronous reset for counter A; a high prevents counting and forces Q1a-Q4a low.
3 Q1a output Parallel binary output bit 1 of counter A (least significant bit).
4 Q2a output Parallel binary output bit 2 of counter A.
5 Q3a output Parallel binary output bit 3 of counter A.
6 Q4a output Parallel binary output bit 4 of counter A (most significant bit).
7 GND power_in Ground reference for the device; all voltages, including VCC and input/output levels, are referenced to this pin.
8 Q4b output Parallel binary output bit 4 of counter B (most significant bit).
9 Q3b output Parallel binary output bit 3 of counter B.
10 Q2b output Parallel binary output bit 2 of counter B.
11 Q1b output Parallel binary output bit 1 of counter B (least significant bit).
12 RESET b input Active-high asynchronous reset for counter B; a high prevents counting and forces Q1b-Q4b low.
13 CLOCK b input Clock input for counter B; the internal flip-flops toggle and the count advances on high-to-low transitions of this input.
14 VCC power_in Positive supply; the recommended DC supply range is 2.0 V to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC 2 6 V 2
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V Upper limit printed as VCC 2
Operating Temperature, All Package Types TA -55 125 C 2
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V (Figure 1) 2
Input Rise and Fall Time tr, tf 0 600 ns VCC = 3.0 V (Figure 1) 2
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V (Figure 1) 2
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V (Figure 1) 2
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V 2
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout -0.5 V Upper limit printed as VCC + 0.5 V 2
DC Input Current, per Pin Iin -20 20 mA 2
DC Output Current, per Pin Iout -25 25 mA 2
DC Supply Current, VCC and GND Pins ICC -50 50 mA 2
Power Dissipation in Still Air, TSSOP Package PD 450 mW Still air; TSSOP package 2
Storage Temperature Tstg -65 150 C 2
Lead Temperature TL 260 C 1 mm from case for 10 seconds; SOIC or TSSOP package 2
Minimum High-Level Input Voltage VIH 1.5 V VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Minimum High-Level Input Voltage VIH 2.1 V VCC = 3.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Minimum High-Level Input Voltage VIH 3.15 V VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Minimum High-Level Input Voltage VIH 4.2 V VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Maximum Low-Level Input Voltage VIL 0.5 V VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Maximum Low-Level Input Voltage VIL 0.9 V VCC = 3.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Maximum Low-Level Input Voltage VIL 1.35 V VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Maximum Low-Level Input Voltage VIL 1.8 V VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ ≤ 20 µA 2
Minimum High-Level Output Voltage VOH 1.9 V VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 2
Minimum High-Level Output Voltage VOH 4.4 V VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 2
Minimum High-Level Output Voltage VOH 5.9 V VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 2
Minimum High-Level Output Voltage VOH 2.2 V VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125 °C column 2
Minimum High-Level Output Voltage VOH 3.7 V VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; 125 °C column 2
Minimum High-Level Output Voltage VOH 5.2 V VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; 125 °C column 2
Maximum Low-Level Output Voltage VOL 0.1 V VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA 3
Maximum Low-Level Output Voltage VOL 0.4 V VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; 125 °C column 3
Maximum Input Leakage Current Iin -1 1 µA VCC = 6.0 V; Vin = VCC or GND; 125 °C column 3
Maximum Quiescent Supply Current (per Package) ICC 160 µA VCC = 6.0 V; Vin = VCC or GND; Iout = 0 µA; 125 °C column 3
Maximum Clock Frequency (50% Duty Cycle) fmax 8 MHz VCC = 2.0 V; CL = 50 pF; 125 °C column 3
Maximum Clock Frequency (50% Duty Cycle) fmax 12 MHz VCC = 3.0 V; CL = 50 pF; 125 °C column 3
Maximum Clock Frequency (50% Duty Cycle) fmax 25 MHz VCC = 4.5 V; CL = 50 pF; 125 °C column 3
Maximum Clock Frequency (50% Duty Cycle) fmax 40 MHz VCC = 6.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q1 tPLH, tPHL 90 ns VCC = 2.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q1 tPLH, tPHL 50 ns VCC = 3.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q1 tPLH, tPHL 36 ns VCC = 4.5 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q1 tPLH, tPHL 31 ns VCC = 6.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q2 tPLH, tPHL 180 ns VCC = 2.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q2 tPLH, tPHL 100 ns VCC = 3.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q2 tPLH, tPHL 55 ns VCC = 4.5 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q2 tPLH, tPHL 48 ns VCC = 6.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q3 tPLH, tPHL 180 ns VCC = 2.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q3 tPLH, tPHL 130 ns VCC = 3.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q3 tPLH, tPHL 70 ns VCC = 4.5 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q3 tPLH, tPHL 58 ns VCC = 6.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q4 tPLH, tPHL 300 ns VCC = 2.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q4 tPLH, tPHL 210 ns VCC = 3.0 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q4 tPLH, tPHL 82 ns VCC = 4.5 V; CL = 50 pF; 125 °C column 3
Maximum Propagation Delay, Clock to Q4 tPLH, tPHL 65 ns VCC = 6.0 V; CL = 50 pF; 125 °C column 3
Maximum Input Capacitance Cin 10 pF 3

CAD (KiCad official)

  • Symbol: MC74HC393ADTR2G
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: mc74hc393adtr2g-etched.step / mc74hc393adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hc393adtr2g.step / mc74hc393adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 cedb075428aea1c7, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF