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TPS61379QWRTERQ1
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Texas Instruments DC-DC Converters, WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS61379QWRTERQ1
Texas Instruments · DC-DC Converters · WQFN-16(3x3)
TPS61379QWRTERQ1 from Texas Instruments, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | IC power supply input, operating range 2.3 V to 14 V (absolute maximum 16 V). |
| 2 | BST | passive | Power supply for high-side N-MOSFET gate drivers; a capacitor (above 0.1 µF) must be connected between this pin and SW. |
| 3 | SW | passive | Switching node of the converter, connected to the drain of the internal low-side FET and the source of the high-side FET (abs max 23 V). |
| 4 | SW | passive | Switching node of the converter, connected to the drain of the internal low-side FET and the source of the high-side FET (abs max 23 V). |
| 5 | MODE/SYNC | input | Mode selection: high gives forced PWM, low or floating gives auto PFM; also accepts an external clock for synchronization (200 kHz to 2.2 MHz). |
| 6 | VCC | power_out | Output of internal 4.8 V regulator (10 mA capability); requires a ceramic capacitor of more than 1 µF to GND. |
| 7 | GND | power_in | Power ground of the IC, connected to the source of the low-side FET. |
| 8 | GND | power_in | Power ground of the IC, connected to the source of the low-side FET. |
| 9 | VO | passive | Output of the isolation FET; connect the load here to achieve input/output isolation (abs max 23 V). |
| 10 | OUT | passive | Drain of the HS FET output; connecting the output here can disable the load disconnect/short protection feature, or short this pin to VO (abs max 23 V). |
| 11 | PG | output | Power good indicator, open-drain output requiring an external pullup (abs max 20 V). |
| 12 | NC | unconnected | No connection pin. |
| 13 | FB | input | Feedback pin; use a resistor divider to set the desired output voltage (abs max 6 V). |
| 14 | COMP | passive | Output of the internal transconductance error amplifier; an external RC network is connected to optimize loop stability and response time. |
| 15 | EN | input | Enable logic input; the device is enabled when pulled above 1.2 V. |
| 16 | FREQ | input | Frequency setting pin; a resistor to GND sets the switching frequency from 200 kHz to 2.2 MHz, and the pin must not be left floating or tied to VCC. |
| 17 | Thermal Pad | power_in | The thermal pad must be connected to the power ground plane for good power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16(3x3) |
| Category | Power Supply Chip |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN voltage | VIN | -0.3 | 16 | V | 5 | ||
| VO, SW, OUT voltage | -0.3 | 23 | V | 5 | |||
| BST voltage | BST | -0.3 | 6 | V | relative to SW: SW + 6 V max | 5 | |
| MODE/SYNC, FB, FREQ, VCC, COMP, EN voltage | -0.3 | 6 | V | 5 | |||
| PG voltage | PG | -0.3 | 20 | V | 5 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM per AEC Q100-002 | 5 | |
| ESD CDM all pins | V(ESD) | -500 | 500 | V | CDM per AEC Q100-011, all pins | 5 | |
| ESD CDM corner pins | V(ESD) | -750 | 750 | V | CDM, corner pins | 5 | |
| Input voltage | VIN | 2.3 | 14 | V | 5 | ||
| Output voltage | VOUT | 4 | 18.5 | V | 5 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 46.2 | °C/W | RTE 16 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 43.5 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 18.5 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 1.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 18.5 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 8.8 | °C/W | 6 | |||
| Input voltage range | VIN | 2.3 | 14 | V | 6 | ||
| VIN UVLO threshold rising | VIN_UVLO | 2.2 | 2.3 | V | VIN rising | 6 | |
| VIN UVLO threshold falling | VIN_UVLO | 2.04 | 2.2 | V | VIN falling | 6 | |
| Quiescent current into VIN pin | IQ | 25 | 35 | µA | IC enabled, no load, VIN = 3.3 V, VOUT = 18.5 V, VFB = VREF + 0.1 V | 6 | |
| Quiescent current into OUT pin | IQ | 10 | 20 | µA | IC enabled, no load, VIN = 3.3 V, VOUT = 18.5 V, VFB = VREF + 0.1 V | 6 | |
| Shutdown current into VIN pin | ISD | 0.6 | 5 | µA | IC disabled, VIN = 14 V, EN = GND | 6 | |
| Leakage current into SW | ISW_LKG | 5 | µA | IC disabled, VIN = OUT = SW = 14 V | 6 | ||
| Reverse leakage current into VO | IVO_LKG | 5 | µA | IC disabled, OUT= VO = 5 V, SW = 0 | 6 | ||
| Output over-voltage protection threshold | VOVP | 19.3 | 20 | 20.5 | V | VIN = 3.3 V, VOUT rising | 6 |
| Reference voltage at FB pin | VREF | 0.788 | 0.8 | 0.812 | V | TJ = -40 to 125°C, RFB = 16.0 kΩ | 6 |
| Fixed output 5 V | VOUT_5V | 4.85 | 5 | 5.15 | V | TJ = -40 to 125°C, RFB = 2.0 kΩ | 6 |
| Fixed output 5.25 V | VOUT_5.25V | 5.1 | 5.25 | 5.35 | V | TJ = -40 to 125°C, RFB = 4.0 kΩ | 6 |
| Fixed output 5.5 V | VOUT_5.5V | 5.35 | 5.5 | 5.65 | V | TJ = -40 to 125°C, RFB = 8.0 kΩ | 6 |
| Leakage current into FB pin | IFB_LKG | 50 | nA | 6 | |||
| Peak switching current limit Auto PFM | ILIM_SW | 1.58 | 2 | 2.25 | A | Auto PFM, Duty cycle = 65% | 6 |
| Peak switching current limit FPWM | ILIM_SW | 1.58 | 2 | 2.25 | A | FPWM, Duty cycle = 65% | 6 |
| Switching frequency | Fsw | 2050 | 2200 | 2400 | kHz | RFREQ = 18 kΩ | 6 |
| Switching frequency | Fsw | 180 | 200 | 230 | kHz | RFREQ = 218 kΩ | 6 |
| PG delay time | tPG_DELAY | 2.5 | 3.4 | 4.3 | ms | 7 | |
| VIN UVLO hysteresis | VIN_HYS | 160 | mV | 6 | |||
| VCC regulation | VCC | 4.8 | V | IVCC = 6 mA, VOUT = 9V | 6 | ||
| Low-side MOSFET on resistance | RDS(on) | 50 | mΩ | VCC = 4.85 V | 6 | ||
| High-side MOSFET on resistance | RDS(on) | 50 | mΩ | VCC = 4.85 V | 6 | ||
| Isolation MOSFET on resistance | RDS(on) | 100 | mΩ | VCC = 4.85 V | 6 | ||
| Thermal shutdown rising threshold | tSD_R | 165 | °C | TJ rising | 7 |
CAD (KiCad official)
- Symbol:
TPS61379QWRTERQ1 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps61379qwrterq1-etched.step/tps61379qwrterq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps61379qwrterq1.step/tps61379qwrterq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
ea20990036694e7f, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).