AD5620CRMZ-1 from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Power supply input; these parts can operate from 2.7 V to 5.5 V and VDD should be decoupled to GND.
2	VREFOUT	output	Reference voltage output; for the AD5620CRMZ-1 this is the internal 1.25 V, 5 ppm/°C reference.
3	VFB	input	Feedback connection for the output amplifier, which should be connected to VOUT for normal operation.
4	VOUT	output	Analog output voltage from the DAC, driven by an output amplifier with rail-to-rail operation.
5	SYNC	input	Level-triggered active-low frame synchronization input; data is shifted in on the falling clock edges while SYNC is low, the DAC updates after the 16th clock, and a rising SYNC before that edge aborts the write.
6	SCLK	input	Serial clock input; data is clocked into the input shift register on the falling edge, at rates up to 30 MHz.
7	DIN	input	Serial data input; the AD5620 has a 16-bit shift register and data is clocked in on the falling edge of SCLK.
8	GND	power_in	Ground reference point for all circuitry on the part.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-8
Category	ADC/DAC/Data Conversion
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Resolution (AD5620)		12			Bits		5
Relative Accuracy (AD5620, C grade)		-1		1	LSB		5
Differential Nonlinearity (AD5620, C grade)		-0.25		0.25	LSB	Guaranteed monotonic by design	5
Zero-Code Error (AD5620, C grade)				8	mV	All 0s loaded to DAC register	5
Offset Error (AD5620, C grade)		-9		9	mV		5
Full-Scale Error (AD5620, C grade)		-0.85		0.85	% FSR		5
Gain Error (AD5620, C grade)		-0.85		0.85	% FSR		5
Output Voltage Range	VOUT	0			V		5
Output Voltage Settling Time (AD5620, C grade)				10	µs	RL = 2 kΩ; 0 pF < CL < 200 pF	5
Reference Output Voltage		1.247		1.253	V	At ambient	5
Reference TC		-15		15	ppm/°C		5
Input Current		-1		1	µA	All digital inputs	6
Input Low Voltage	VINL			0.8	V	VDD = 3 V	6
Input High Voltage	VINH	2			V	VDD = 3 V	6
Pin Capacitance				3	pF		6
VDD Supply Voltage (minimum)	VDD	2.7			V	All digital inputs at 0 V or VDD	6
VDD Supply Voltage (maximum)	VDD			3.3	V	DAC active and excluding load current	6
IDD (Normal Mode)	IDD			0.65	mA	VDD = 2.7 V to 3.3 V; VIH = VDD and VIL = GND	6
IDD (All Power-Down Modes)	IDD			0.25	µA	VDD = 2.7 V to 3.3 V; VIH = VDD and VIL = GND	6
VDD to GND	VDD	-0.3		7	V		8
VOUT to GND	VOUT	-0.3			V	Maximum printed as VDD + 0.3 V	8
VFB to GND	VFB	-0.3			V	Maximum printed as VDD + 0.3 V	8
VREFOUT to GND	VREFOUT	-0.3			V	Maximum printed as VDD + 0.3 V	8
Digital Input Voltage to GND		-0.3			V	Maximum printed as VDD + 0.3 V	8
Operating Temperature Range (Industrial)		-40		105	°C		8
Storage Temperature Range		-65		150	°C		8
Junction Temperature (TJ max)	TJ			150	°C		8
Reflow Soldering Peak Temperature (SnPb)				240	°C		8
Reflow Soldering Peak Temperature (Pb-Free)				260	°C		8
SCLK cycle time	t1	50			ns	VDD = 2.7 V to 3.6 V	7
SCLK high time	t2	13			ns	VDD = 2.7 V to 3.6 V	7
SCLK low time	t3	13			ns	VDD = 2.7 V to 3.6 V	7
SYNC to SCLK falling edge setup time	t4	13			ns	VDD = 2.7 V to 3.6 V	7
Data setup time	t5	5			ns	VDD = 2.7 V to 3.6 V	7
Data hold time	t6	4.5			ns	VDD = 2.7 V to 3.6 V	7
SCLK falling edge to SYNC rising edge	t7	0			ns	VDD = 2.7 V to 3.6 V	7
Minimum SYNC high time	t8	50			ns	VDD = 2.7 V to 3.6 V	7
SYNC rising edge to SCLK fall ignore	t9	13			ns	VDD = 2.7 V to 3.6 V	7
SCLK falling edge to SYNC fall ignore	t10	0			ns	VDD = 2.7 V to 3.6 V	7
Thermal Impedance, junction-to-ambient (MSOP)	θJA		141		°C/W	MSOP package, 4-layer board	8
Thermal Impedance, junction-to-case (MSOP)	θJC		44		°C/W	MSOP package	8

CAD (KiCad official)

Symbol: AD5620CRMZ-1
Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
3D model: MSOP-8 (KiCad packages3D, STEP)
3D model files: ad5620crmz-1-etched.step / ad5620crmz-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5620crmz-1.step / ad5620crmz-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 f2131f1417ffb106, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5620CRMZ-1

Verified AD5620CRMZ-1

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README