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Contents

README

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ICL3232IVZ

RENESAS · Pre-ordered Chips · TSSOP-16

ICL3232IVZ from RENESAS, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C1+ passive External capacitor (voltage doubler) is connected to this lead.
2 V+ power_out Internally generated positive transmitter supply (+5.5V).
3 C1- passive External capacitor (voltage doubler) is connected to this lead.
4 C2+ passive External capacitor (voltage inverter) is connected to this lead.
5 C2- passive External capacitor (voltage inverter) is connected to this lead.
6 V- power_out Internally generated negative transmitter supply (-5.5V).
7 T2OUT output RS-232 level (nominally ±5.5V) transmitter output.
8 R2IN input RS-232 compatible receiver input.
9 R2OUT output TTL/CMOS level receiver output.
10 T2IN input TTL/CMOS compatible transmitter input.
11 T1IN input TTL/CMOS compatible transmitter input.
12 R1OUT output TTL/CMOS level receiver output.
13 R1IN input RS-232 compatible receiver input.
14 T1OUT output RS-232 level (nominally ±5.5V) transmitter output.
15 GND power_in Ground connection.
16 VCC power_in System power supply input (3.0V to 5.5V).

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC (system power supply input) VCC 3 5.5 V Pin description: system power supply input 8
Operating Temperature Range (ICL32xxIx) -40 85 °C ICL32xxIx 10
VCC to Ground VCC -0.3 6 V 9
V+ to Ground V+ -0.3 7 V 9
V- to Ground V- 0.3 -7 V 9
V+ to V- 14 V 9
Input Voltages TIN, FORCEOFF, FORCEON, EN, SHDN -0.3 6 V 9
Input Voltage RIN -25 25 V 9
Output Voltage TOUT -13.2 13.2 V 9
Maximum Junction Temperature (Plastic Package) 150 °C 9
Maximum Storage Temperature Range -65 150 °C 9
Supply Current, Automatic Power-Down Disabled 0.3 1 mA 25°C; all outputs unloaded, FORCEON = FORCEOFF = SHDN = VCC, VCC = 3.15V 10
Input Logic Threshold Low 0.8 V Full temperature range 10
Input Logic Threshold High 2 V VCC = 3.3V, Full temperature range 10
Input Logic Threshold High 2.4 V VCC = 5.0V, Full temperature range 10
Input Leakage Current -1 1 µA TIN, FORCEON, FORCEOFF, EN, SHDN; Full temperature range 10
Output Voltage Low 0.4 V IOUT = 1.6mA, Full temperature range 10
Receiver Input Voltage Range -25 25 V Full temperature range 10
Receiver Input Threshold Low 0.6 1.2 V VCC = 3.3V, 25°C 10
Receiver Input Threshold Low 0.8 1.5 V VCC = 5.0V, 25°C 10
Receiver Input Threshold High 1.5 2.4 V VCC = 3.3V, 25°C 10
Receiver Input Threshold High 1.8 2.4 V VCC = 5.0V, 25°C 10
Input Resistance 3 5 7 kΩ 25°C 11
Output Voltage Swing -5 V All transmitter outputs loaded with 3kΩ to ground; Full temperature range 11
Output Resistance 300 W VCC = V+ = V- = 0V, transmitter output = ±2V; Full temperature range 11
Output Short-Circuit Current -60 60 mA Full temperature range 11
Output Leakage Current -25 25 µA VOUT = ±12V, VCC = 0V or 3V to 5.5V; Automatic Powerdown or FORCEOFF = SHDN = GND; Full temperature range 11
Maximum Data Rate 250 500 kbps RL = 3kΩ, CL = 1000pF, one transmitter switching; Full temperature range 11
Transition Region Slew Rate 4 8 30 V/µs VCC = 3.3V, RL = 3kΩ to 7kΩ, measured from 3V to -3V or -3V to 3V, CL = 200pF to 2500pF, 25°C 11
Transition Region Slew Rate 6 30 V/µs CL = 200pF to 1000pF, 25°C 11
Receiver Skew tPHL - tPLH 100 500 ns Full temperature range 11
Thermal Resistance θJA, 16 Ld TSSOP Package θJA 145 °C/W Typical, Note 4 (low-effective thermal conductivity test board, free air) 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin C2- External capacitor (voltage inverter) is connected to this lead. TIN TTL/CMOS compatible transmitter Inputs. 8

CAD (KiCad official)

  • Symbol: ICL3232IVZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: icl3232ivz-etched.step / icl3232ivz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); icl3232ivz.step / icl3232ivz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (36 pp, sha256 b2a9e9447525ad5b, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF