UC2844AQD8R-TUDI from Tudi, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Output of the low-impedance 1-MHz internal error amplifier, which is also the input to the peak current limit or PWM comparator, with an open-loop gain (AVOL) of 80 dB; it can sink a maximum of 6 mA and is not internally current limited.
2	FB	input	Input to the error amplifier that can be used to control the power converter voltage-feedback loop for stability.
3	ISENSE	input	Input to the peak current limit and PWM comparator, where the maximum peak current sense signal is internally clamped to 1 V.
4	RT/CT	input	Input to the internal oscillator programmed by an external timing resistor (RT) and timing capacitor (CT); TUDI recommends CT from 470 pF to 4.7 nF and RT from 5 kΩ to 100 kΩ.
5	GND	power_in	This is the controller signal ground.
6	OUTPUT	output	Output of the 1-A totem-pole gate driver that can sink and source up to 1 A of gate driver current, and a gate driver resistor must be used to limit that current.
7	VCC	power_in	Bias input to the gate driver, which must have a biasing capacitor at least 10 times greater than the gate capacitance of the main switching FET used in the design.
8	VREF	power_out	Reference voltage output that must supply no more than 10 mA under normal operation, is short-circuit protected at roughly 100 mA, and needs a 1 µF high-frequency bypass capacitor with the VCC capacitor at least 10 times larger.

Key specifications

Parameter	Value
Manufacturer	Tudi
Package	SOP-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (low impedance source), VCC pin				30	V		5
Output current	IOUT	-1		1	A		5
Output energy (capacitive load)				5	μJ		5
Analog inputs		-0.3		6.3	V		5
Maximum negative voltage, all pins		-0.3			V		5
Error amplifier output sink current	ICOMP			10	mA		5
Power dissipation at TA				1	W	TA 25	5
Lead temperature (soldering, 10 s)				300	°C	10 s soldering	5
Junction temperature	TJ	-55		150	°C		5
Storage temperature	Tstg	-65		150	°C		5
ESD, human-body model (HBM)	V(ESD)	-2000		2000	V	HBM, per ANSI/ESDA/JEDEC JS-001	5
ESD, charged-device model (CDM)	V(ESD)	-1500		1500	V	CDM, per JEDEC JESD22-C101	5
Voltage on analog pins		-0.1			V	FB, ISENSE and RT/CT pins	6
Gate driver output voltage	VOUT	-0.1			V	Printed upper limit is VCC (not a number)	6
Output current, reference	IVREF			10	mA	VREF pin	6
Oscillator frequency	fOSC			500	kHz		6
Operating free-air temperature, UC284xA	TA	-40		85	°C	UC284xA	6
Junction-to-ambient thermal resistance, SOIC (D)	RθJA		117.4		°C/W	D (SOIC) column	6
Output voltage		4.95	5	5.05	V	TJ=25°C, IO=1mA; UC284xA	7
Line regulation		6		20	mV	12 VIN 25V	7
Load regulation		6		25	mV	1 IO 20 mA	7
Temperature stability		0.2		0.4	mV	See (1)(6)	7
Total output variation		4.9		5.1	V	Line, Load, Temperature; UC284xA	7
Long-term stability		5		25	mV	TA=125°C, 1000 hrs	7
Output short circuit		-30	-100	-180	mA		7
Initial accuracy		47	52	57	kHz	TJ=25°C	7
Voltage stability		0.2		1	%	12 VCC 25V	7
Discharge current		7.8	8.3	8.8	mA	TJ=25°C, VRT/CT=2V	7
Discharge current, UC284xA		7.5		8.8	mA	VRT/CT=2V; UC284xA	7
Input voltage		2.45	2.5	2.55	V	VCOMP=2.5V; UC284xA	7
Input bias current		-0.3		-1	μA		7
Open-loop gain	AVOL	65		90	dB	2 Vo 4V	7
Unity gain bandwidth		0.7		1	MHz	TJ=25°C	7
Common mode rejection ratio	CMRR	60		70	dB	12 VCC 25V	7
Output sink current		2		6	mA	VFB=2.7V, VCOMP=1.1V	7
Output source current		-0.5		-0.8	mA	VFB=2.3V, VCOMP=5V	7
VOUT high		5		6	V	VFB=2.3V, RL=15k to ground	7
VOUT low		0.7		1.1	V	VFB=2.7V, RL=15k to VREF	7
Gain		2.85	3	3.15	VIN	See (2)(3)	8
Maximum input signal		0.9	1	1.1	V	VCOMP=5V	8
Input bias current, current sense		-2		-10	μA		8
Delay to output		150		300	ns	VISENSE=0 to 2V	8
Output low level		0.1		0.4	V	ISINK=20 mA	8
Output low level		1.5		2.2	V	ISINK=200 mA	8
Output high level		13		13.5	V	ISOURCE=20 mA	8
Output high level		12		13.5	V	ISOURCE=200 mA	8
Rise time		25		150	ns	TJ=25°C, CL=1nF	8
Fall time		25		150	ns	TJ=25°C, CL=1nF	8
UVLO saturation		0.7		1.2	V	VCC=5V, ISINK=10 mA	8
Start threshold, UC2844A		15	16	17	V	UC2842A and UC2844A	8
Minimum operation voltage after turnon, UC2844A		9	10	11	V	UC2842A and UC2844A	8
Maximum duty cycle, UCx844A		46	48	50	%	UCx844A, UCx845A	8
Minimum duty cycle		0			%		8
Start-up current		0.3		0.5	mA		8
Operating supply current		11		17	mA	VFB=VISENSE=0V	8
VCC Zener voltage		30		39	V	ICC=25 mA	8

CAD (KiCad official)

Symbol: UC2844AQD8R-TUDI
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: uc2844aqd8r-tudi-etched.step / uc2844aqd8r-tudi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2844aqd8r-tudi.step / uc2844aqd8r-tudi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Tudi datasheet (16 pp, sha256 d1c80fc1b58b578b, retrieved 2026-11-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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UC2844AQD8R-TUDI

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