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STM8AF6223PCX

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by Ray

STMicroelectronics Microcontrollers (MCU/MPU/SOC), TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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STM8AF6223PCX

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · TSSOP-20

STM8AF6223PCX from STMicroelectronics, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD4/TIM5_CH1/BEEP/[LINUART_CK] bidirectional General-purpose I/O Port D4 (high-sink, O3 speed, floating/pull-up input, OD/PP output). Default alternate: TIM5_CH1 or BEEP output; remap [AFR2] gives LINUART clock.
2 PD5/AIN5/LINUART_TX bidirectional General-purpose I/O Port D5 (high-sink, O3 speed). Default alternate functions: analog input AIN5 for the 10-bit ADC and LINUART data transmit (TX).
3 PD6/AIN6/LINUART_RX bidirectional General-purpose I/O Port D6 (high-sink, O3 speed). Default alternate functions: analog input AIN6 for the 10-bit ADC and LINUART data receive (RX).
4 NRST bidirectional Active-low bidirectional reset pin with internal pull-up. Drive low externally to reset the MCU; internally driven low by watchdog/POR events. Requires filtering per Figure 35 recommended reset protection.
5 PA1/OSCIN bidirectional General-purpose I/O Port A1 or HSE crystal/resonator oscillator input (OSCIN). Slow output speed (O1). In Halt/Active-halt PA1 is auto-configured as input weak pull-up and cannot wake the device.
6 PA2/OSCOUT bidirectional General-purpose I/O Port A2 or HSE crystal/resonator oscillator output (OSCOUT). Slow output speed (O1).
7 VSS power_in Digital ground reference (0 V). Connect to the system ground plane with low-impedance return.
8 VCAP passive Internal 1.8 V core regulator output stabilization pin. Requires an external decoupling capacitor to VSS (typ. 1 uF ceramic) - do not connect to any supply rail.
9 VDD power_in Digital power supply, 3.0 V to 5.5 V operating range. Decouple to VSS with 100 nF (plus bulk capacitance) close to the pin.
10 PA3/TIM5_CH3/[SPI_NSS] bidirectional General-purpose I/O Port A3 (high-sink, O3 speed). Default alternate: TIM5 channel 3; remap [AFR1] gives SPI slave-select NSS.
11 PB5/I2C_SDA/[TIM1_BKIN] bidirectional Port B5 configured as true open-drain I/O (no P-buffer, no weak pull-up, no protection diode to VDD). Default alternate: I2C data (SDA); remap [AFR4] gives TIM1 break input.
12 PB4/I2C_SCL/[ADC_ETR] bidirectional Port B4 configured as true open-drain I/O. Default alternate: I2C clock (SCL); remap [AFR4] gives ADC external trigger.
13 PC3/TIM1_CH3/[TLI]/[TIM1_CH1N] bidirectional General-purpose I/O Port C3 (high-sink, O3 speed). Default alternate: TIM1 channel 3; remap [AFR3] gives TLI (top-level interrupt); remap [AFR7] gives TIM1 inverted channel 1.
14 PC4/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N] bidirectional General-purpose I/O Port C4 (high-sink, O3 speed). Default alternates: TIM1 channel 4 or configurable clock output (CCO); remap [AFR2] gives ADC analog input AIN2; remap [AFR7] gives TIM1 inverted channel 2.
15 PC5/SPI_SCK/[TIM5_CH1] bidirectional Port C5 (high-sink, O3 speed). Default alternate: SPI clock (SCK); remap [AFR0] gives TIM5 channel 1.
16 PC6/SPI_MOSI/[TIM1_CH1] bidirectional Port C6 (high-sink, O3 speed). Default alternate: SPI MOSI (master-out/slave-in); remap [AFR0] gives TIM1 channel 1.
17 PC7/SPI_MISO/[TIM1_CH2] bidirectional Port C7 (high-sink, O3 speed). Default alternate: SPI MISO (master-in/slave-out); remap [AFR0] gives TIM1 channel 2.
18 PD1/SWIM bidirectional Port D1 (high-sink, O4 fast-default speed) doubling as the SWIM single-wire debug/programming data interface. PD1 is input pull-up during the reset phase and after internal reset release.
19 PD2/AIN3/[TIM5_CH3] bidirectional General-purpose I/O Port D2 (high-sink, O3 speed). Remap [AFR2] gives ADC analog input AIN3; remap [AFR1] gives TIM5 channel 3.
20 PD3/AIN4/TIM5_CH2/ADC_ETR bidirectional General-purpose I/O Port D3 (high-sink, O3 speed). Default alternate: analog input AIN4 / TIM5 channel 2 / ADC external trigger.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TSSOP-20
Category Embedded Processors & Controllers
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • STM8AF6223PCX
  • STM8AF6223PCXPCY
  • STM8AF6223PCXPCU
  • STM8AF6223PCXPAX
  • STM8AF6223PCXPAY
  • STM8AF6223PCXPAU
  • STM8AF6223PCXPDX
  • STM8AF6223PCXPDY
  • STM8AF6223PCXPDU

CAD (KiCad official)

  • Symbol: STM8AF6223PCX
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (110 pp, sha256 ffb367d8b93062e4, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF