component
TPS65321AQPWPRQ1
Public Made by Adomby adom
Texas Instruments Linear Voltage Regulators (LDO), TSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPS65321AQPWPRQ1
Texas Instruments · Linear Voltage Regulators (LDO) · TSSOP-14-EP
TPS65321AQPWPRQ1 from Texas Instruments, in a TSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap capacitor is required between BOOT and SW to supply the bias voltage for the integrated high-side MOSFET (abs max 46 V, BOOT-SW 8 V). |
| 2 | VIN | power_in | Input supply pin for the internal biasing and high-side MOSFET of the buck regulator, 3.6 V to 36 V input range (abs max 40 V). |
| 3 | VIN_LDO | power_in | Input supply pin for the LDO regulator, 3 V to 36 V input range (abs max 40 V). |
| 4 | LDO_OUT | power_out | LDO regulator output, 280 mA capability, adjustable 1.1 V to 5.5 V (abs max 7 V). |
| 5 | FB2 | input | Feedback pin of the LDO regulator; connect an external resistive divider between LDO_OUT, FB2 and GND to set the LDO output voltage. |
| 6 | nRST | output | Active-low open-drain reset output of the buck regulator; connect to an external bias voltage through a resistor, asserted high after the buck begins regulating. |
| 7 | EN2 | input | Enable input for the LDO regulator, high-voltage tolerant and internally pulled to ground; pull up externally to enable. |
| 8 | EN1 | input | Enable input for the buck regulator, high-voltage tolerant and internally pulled to ground; pull up externally to enable. |
| 9 | RT/CLK | input | Connect an external resistor to ground to program the buck switching frequency, or feed an external clock as the switching frequency reference. |
| 10 | SS | input | Connect an external capacitor to ground to set the soft-start time of the buck regulator. |
| 11 | FB1 | input | Feedback pin of the buck regulator; connect an external resistive divider from the buck output to GND to set the output voltage. |
| 12 | COMP | output | Error-amplifier output of the buck regulator and input to the output switch-current comparator; connect frequency-compensation components here. |
| 13 | GND | power_in | Ground pin. |
| 14 | SW | output | Source node of the internal high-side MOSFET of the buck regulator (abs max 40 V). |
| 15 | PowerPAD | power_in | Exposed thermal pad; electrically connect to ground and solder to the PCB ground plane for thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14-EP |
| Category | Power Supply Chip |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN supply input voltage | VIN | -0.3 | 40 | V | 4 | ||
| VIN_LDO supply input voltage | VIN_LDO | -0.3 | 40 | V | 4 | ||
| Control pins EN1, EN2 | EN1, EN2 | -0.3 | 40 | V | 4 | ||
| Buck feedback pin FB1 | FB1 | -0.3 | 3.6 | V | 4 | ||
| Buck switch node SW | SW | -0.3 | 40 | V | 4 | ||
| Buck BOOT pin | BOOT | -0.3 | 46 | V | 4 | ||
| Buck BOOT-SW voltage | BOOT-SW | 8 | V | 4 | |||
| Buck error amplifier output COMP | COMP | -0.3 | 3.6 | V | 4 | ||
| Buck soft-start pin SS | SS | -0.3 | 3.6 | V | 4 | ||
| Buck RT/CLK pin | RT/CLK | -0.3 | 3.6 | V | 4 | ||
| Reset output nRST | nRST | -0.3 | 7 | V | 4 | ||
| LDO output LDO_OUT | LDO_OUT | -0.3 | 7 | V | 4 | ||
| LDO feedback pin FB2 | FB2 | -0.3 | 7 | V | 4 | ||
| Operating ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 165 | °C | 4 | ||
| Supply input VIN (recommended) | VIN | 3.6 | 36 | V | 5 | ||
| Supply input VIN_LDO (recommended) | VIN_LDO | 3 | 36 | V | 5 | ||
| Buck BOOT pin (recommended) | BOOT | 3.6 | 42 | V | 5 | ||
| Buck switch node SW1 (recommended) | SW1 | -1 | 36 | V | 5 | ||
| Buck feedback FB1 (recommended) | FB1 | 0 | 0.8 | V | 5 | ||
| Buck soft-start SS (recommended) | SS | 0 | 3 | V | 5 | ||
| Buck COMP (recommended) | COMP | 0 | 3 | V | 5 | ||
| Buck RT/CLK (recommended) | RT/CLK | 0 | 3 | V | 5 | ||
| Reset output nRST (recommended) | nRST | 0 | 5.25 | V | 5 | ||
| LDO output LDO_OUT (recommended) | LDO_OUT | 1.1 | 5.5 | V | 5 | ||
| LDO feedback FB2 (recommended) | FB2 | 0 | 0.8 | V | 5 | ||
| Enable EN1 (recommended) | EN1 | 0 | 36 | V | 5 | ||
| Enable EN2 (recommended) | EN2 | 0 | 36 | V | 5 | ||
| Operating junction temperature range (recommended) | TJ | -40 | 150 | °C | 5 | ||
| Operating input voltage | 3.6 | 12 | 36 | V | Normal mode, after initial start-up | 6 | |
| Shutdown supply current | 2 | 7 | μA | V(EN1) = V(EN2) = 0 V, 25°C | 6 | ||
| Enable low level | 0.7 | V | 6 | ||||
| Enable high level | 2.5 | V | 6 | ||||
| Internal UVLO falling threshold | V(VIN)(f) | 1.8 | 2.6 | 3 | V | Ramp V(VIN) down until output turns OFF | 6 |
| Internal UVLO rising threshold | V(VIN)(r) | 2.2 | 2.8 | 3.2 | V | Ramp V(VIN) up until output turns ON | 6 |
| Operating non-switching supply current (buck) | I(Qon) | 110 | 140 | μA | Measured at the VIN pin, V(FB1) = 0.83 V, V(VIN) = 12 V, 25°C | 6 | |
| Buck voltage reference for FB1 | V(ref1) | 0.788 | 0.8 | 0.812 | V | Buck regulator output: 1.1 V to 20 V. Buck regulator in Continuous Conducting Mode without Pulse-Skipping | 6 |
| DC output voltage accuracy | -2 | 2 | % | Includes voltage references, DC load and line regulation, process and temperature | 6 | ||
| Buck high-side MOSFET on-resistance | r(DS(on) HS FET) | 127 | 250 | mΩ | V(VIN) = 12 V, V(SW) = 6 V | 6 | |
| Buck current-limit threshold | 4 | 6 | A | V(VIN) = 12 V, TJ = 25°C | 6 | ||
| Buck switching frequency range (RT mode) | ƒS | 100 | 2500 | kHz | Under RT mode | 6 | |
| Buck switching frequency (fixed-frequency PWM, 200 kΩ RT) | ƒS | 523 | 585 | 640 | kHz | Under fixed-frequency PWM mode, with 200 kΩ connected between RT/CLK and GND pins | 6 |
| Buck switching frequency range (CLK mode) | ƒS | 300 | 2200 | kHz | Under CLK mode | 6 | |
| RT/CLK high threshold | 1.9 | 2.2 | V | 6 | |||
| RT/CLK low threshold | 0.5 | 0.7 | V | 6 | |||
| Initial start-up voltage | 6 | 36 | V | 6 | |||
| LDO line regulation | ΔVO(ΔVI) | 20 | mV | V(VIN_LDO) = 6 V to 30 V, I(LDO_OUT) = 10 mA, V(LDO_OUT) = 3.3 V | 6 | ||
| LDO dropout voltage (V(VIN_LDO), V(LDO_OUT)) | VDROPOUT | 300 | 450 | mV | I(LDO_OUT) = 200 mA | 7 | |
| LDO output current | I(LDO_OUT) | 280 | mA | V(LDO_OUT) in regulation, V(VIN) ≥ 4V | 7 | ||
| Operating input voltage on VIN_LDO pin | VI(VIN_LDO) | 3 | 36 | V | V(LDO_OUT) in regulation | 7 | |
| LDO voltage reference at FB2 | V(ref2) | 0.788 | 0.8 | 0.812 | V | V(LDO_OUT) = 1.1 V to 5.5 V | 7 |
| LDO output current-limit | ICL(LDO_OUT) | 280 | 1000 | mA | V(LDO_OUT) = 0 V (the LDO_OUT pin is shorted to ground) | 7 | |
| LDO quiescent current | IQ(LDO) | 35 | 50 | μA | V(VIN) = 12 V, measured at VIN pin, V(EN1) = 0 V, V(EN2) = 5 V, I(LDO_OUT) = 0.01 mA to 0.75 mA | 7 | |
| LDO output capacitor (V(LDO_OUT) ≥ 3.3 V) | C(LDO_OUT) | 1 | 40 | μF | ESR = 0.001 Ω to 100 mΩ; V(LDO_OUT) ≥ 3.3 V | 7 | |
| Buck soft-start discharge current at 25°C | IDischarge(SS) | 50 | 400 | μA | V(SS) = 1 V, EN1 = 0, TA = 25°C | 6 | |
| Buck nRST reset threshold | 85 | 90 | 95 | % | V(FB1) decreasing | 7 | |
| Thermal resistance junction-to-ambient | RθJA | 41 | °C/W | 5 | |||
| Thermal resistance junction-to-board | RθJB | 25.4 | °C/W | 5 | |||
| Thermal resistance junction-to-case (bottom) | RθJC(bot) | 2.7 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS65321AQPWPRQ1 - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-14-EP (KiCad packages3D, STEP)
- 3D model files:
tps65321aqpwprq1-etched.step/tps65321aqpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65321aqpwprq1.step/tps65321aqpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (46 pp, sha256
730705a404b718e6, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).