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SS6209L-SO-TP

Public Made by Adom

by adom

LEADPOWER Gate Drivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SS6209L-SO-TP

LEADPOWER · Gate Drivers · SOP-8

SS6209L-SO-TP from LEADPOWER, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST passive Bootstrap voltage pin for the high-side driver supply; absolute maximum -0.3 to 35 V, and BST to SW max 6.5 V.
2 PWM input PWM logic input compatible with 3.3V and 5V; high threshold min 1.2 V, low threshold max 1.0 V, abs max 6.5 V, 500 kΩ typical pull-down.
3 EN input Standby-mode logic input (low puts the device in low quiescent current state); high threshold min 1.2 V, low threshold max 1.0 V, abs max 6.5 V, 500 kΩ typical pull-down.
4 VDD power_in Logic and gate driver supply voltage; recommended 3.3 V to 5.5 V, abs max 6.5 V.
5 SW output Switch node output; recommended 0 to 28 V, abs max -0.3 to 28 V.
6 NA unconnected No connect (empty pin).
7 PGND power_in Power ground.
8 VB power_in Power supply input; recommended 3.3 V to 28 V, abs max -0.3 to 30 V.

Key specifications

Parameter Value
Manufacturer LEADPOWER
Package SOP-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic and gate driver supply voltage VDD -0.3 6.5 V 4
Power supply input VB -0.3 30 V 4
Bootstrap voltage BST -0.3 35 V 4
Switch node output SW -0.3 28 V 4
BST to SW BST to SW -0.3 6.5 V 4
PWM logic input PWM -0.3 6.5 V 4
EN standby logic input EN -0.3 6.5 V 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature TS -40 150 °C 4
Soldering temperature TL 260 °C duration 10s 4
Logic and gate driver supply voltage VDD 3.3 5.5 V 4
Power supply input VB 3.3 28 V 4
Switch node output SW 0 28 V 4
Operating junction temperature TJ -30 85 °C 4
VDD undervoltage positive threshold VDDUV+ 2 2.2 2.6 mA TA=25℃, VDD=5V 5
PWM high-level voltage VINH 1.2 V VB=24V, VDD=3.3V 5
PWM low-level voltage VINL 1 V VB=24V, VDD=3.3V 5
EN high-level voltage VINH 1.2 V VB=24V, VDD=3.3V 5
EN low-level voltage VINL 1 V VB=24V, VDD=3.3V 5
VDD quiescent current in standby IQVDD 20 uA VB=24V, PWM=20kHz, EN=0 5
VDD UVLO hysteresis VDDHYS 0.2 V 5
PWM input hysteresis VPWMHYS 0.2 V VB=24V, VDD=3.3V 5
PWM pull-down resistance RIN 500 kΩ VB=24V, VDD=3.3V 5
EN input hysteresis VENHYS 0.2 V VB=24V, VDD=3.3V 5
EN pull-down resistance RIN 500 kΩ VB=24V, VDD=3.3V 5
Overtemperature protection point 170 °C 5
Overtemperature hysteresis 25 °C 5
High-side on-resistance RDS(ON) 15 mΩ VB=24V, VDD=3.3V 5
Low-side on-resistance RDS(ON) 15 mΩ VB=24V, VDD=3.3V 5
Minimum low-side on-time in PWM period toff(PWM) 500 ns VB=24V, VDD=3.3V, RBST = 1Ω, CBST= 100nF 5

CAD (KiCad official)

  • Symbol: SS6209L-SO-TP
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ss6209l-so-tp-etched.step / ss6209l-so-tp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ss6209l-so-tp.step / ss6209l-so-tp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LEADPOWER datasheet (6 pp, sha256 e28987f5fc29f70f, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF