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AD9245BCPZ-20
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Analog Devices Analog To Digital Converters (ADC), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD9245BCPZ-20
Analog Devices · Analog To Digital Converters (ADC) · LFCSP-32(5x5)
AD9245BCPZ-20 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DNC | unconnected | Do not connect; this pin must not be connected to anything. |
| 2 | CLK | input | Single-ended clock input that controls all internal conversion cycles, with the duty-cycle stabilizer compensating for clock duty-cycle variation. |
| 3 | DNC | unconnected | Do not connect; this pin must not be connected to anything. |
| 4 | PDWN | input | Power-down function select input; Table 9 gives no further limits for this pin. |
| 5 | D0 | output | Data output bit D0 (LSB) of the 14-bit parallel output word, with format set by the MODE pin. |
| 6 | D1 | output | Data output bit D1 of the 14-bit parallel output word, with format set by the MODE pin. |
| 7 | D2 | output | Data output bit D2 of the 14-bit parallel output word, with format set by the MODE pin. |
| 8 | D3 | output | Data output bit D3 of the 14-bit parallel output word, with format set by the MODE pin. |
| 9 | D4 | output | Data output bit D4 of the 14-bit parallel output word, with format set by the MODE pin. |
| 10 | D5 | output | Data output bit D5 of the 14-bit parallel output word, with format set by the MODE pin. |
| 11 | D6 | output | Data output bit D6 of the 14-bit parallel output word, with format set by the MODE pin. |
| 12 | D7 | output | Data output bit D7 of the 14-bit parallel output word, with format set by the MODE pin. |
| 13 | D8 | output | Data output bit D8 of the 14-bit parallel output word, with format set by the MODE pin. |
| 14 | D9 | output | Data output bit D9 of the 14-bit parallel output word, with format set by the MODE pin. |
| 15 | DGND | power_in | Digital output ground for the output driver circuitry. |
| 16 | DRVDD | power_in | Digital output driver supply, specified at 2.25 V to 3.6 V (Table 1), allowing 2.5 V or 3.3 V logic families. |
| 17 | D10 | output | Data output bit D10 of the 14-bit parallel output word, with format set by the MODE pin. |
| 18 | D11 | output | Data output bit D11 of the 14-bit parallel output word, with format set by the MODE pin. |
| 19 | D12 | output | Data output bit D12 of the 14-bit parallel output word, with format set by the MODE pin. |
| 20 | D13 | output | Data output bit D13 (MSB) of the 14-bit parallel output word, with format set by the MODE pin. |
| 21 | OTR | output | Out-of-range indicator that signals when the analog input is beyond the selected input range, usable with the MSB to determine low or high overflow. |
| 22 | MODE | input | Selects the data format (offset binary or twos complement) and the clock duty-cycle stabilizer mode; see Table 11 for settings. |
| 23 | SENSE | input | Selects the reference mode; see Table 10 for settings (1.0 V or 0.5 V internal reference operation per Table 1). |
| 24 | VREF | power_in | Voltage reference input/output pin; the internal reference is 1.0 V in the 1 V mode and gives a 2 V p-p input span. |
| 25 | REFB | passive | Differential reference negative (-) node. |
| 26 | REFT | passive | Differential reference positive (+) node. |
| 27 | AVDD | power_in | Analog power supply, specified at 2.7 V to 3.6 V (Table 1). |
| 28 | AGND | power_in | Analog ground. |
| 29 | VIN+ | power_in | Analog differential input pin (+), accepting a 1 V p-p to 2 V p-p input range set by the reference mode. |
| 30 | VIN- | power_in | Analog differential input pin (-), accepting a 1 V p-p to 2 V p-p input range set by the reference mode. |
| 31 | AGND | power_in | Analog ground. |
| 32 | AVDD | power_in | Analog power supply, specified at 2.7 V to 3.6 V (Table 1). |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-32(5x5) |
| Category | Data Acquisition |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Offset Error | -1.6 | 1.6 | % FSR | 3 | |||
| Gain Error | -3.25 | 3.25 | % FSR | Footnote 1: ADC only, fixed 1.0 V external reference | 3 | ||
| Differential Nonlinearity (DNL) | DNL | -1 | 1 | LSB | 3 | ||
| Integral Nonlinearity (INL) | INL | -3.1 | 3.1 | LSB | 3 | ||
| Temperature Drift Offset Error | -2 | 2 | ppm/°C | 3 | |||
| Temperature Drift Gain Error | -12 | 12 | ppm/°C | 3 | |||
| Output Voltage Error (1 V Mode) | -35 | 35 | mV | 3 | |||
| Output Voltage Error (0.5 V Mode) | -2.5 | 2.5 | mV | 3 | |||
| PSRR | -0.01 | 0.01 | % FSR | 3 | |||
| AVDD Supply Voltage | AVDD | 2.7 | 3 | 3.6 | V | 3 | |
| DRVDD Supply Voltage | DRVDD | 2.25 | 3 | 3.6 | V | 3 | |
| Operating Temperature Range | -40 | 85 | °C | 9 | |||
| Supply Current IAVDD | IAVDD | 30 | mA | 3 | |||
| Supply Current IDRVDD | IDRVDD | 2 | mA | 3 | |||
| Load Regulation @ 1.0 mA | 0.8 | mV | @ 1.0 mA | 3 | |||
| Load Regulation @ 0.5 mA | 0.1 | mV | @ 0.5 mA | 3 | |||
| Input Referred Noise | 2.28 | LSB rms | VREF = 0.5 V | 3 | |||
| Input Referred Noise | 1.08 | LSB rms | VREF = 1.0 V | 3 | |||
| Input Span | 1 | V p-p | VREF = 0.5 V | 3 | |||
| Input Span | 2 | V p-p | VREF = 1.0 V | 3 | |||
| Input Capacitance | 7 | pF | Effective capacitance between one differential input pin and AGND | 3 | |||
| Reference Input Resistance | 7 | kΩ | 3 | ||||
| Power Consumption DC Input | 90 | mW | DC input at maximum clock rate | 3 | |||
| Power Consumption Sine Wave Input | 95 | 120 | mW | Sine wave input | 3 | ||
| Standby Power | 1 | mW | DC input, CLK pin inactive | 3 | |||
| Resolution | 14 | Bits | 3 | ||||
| Maximum Conversion Rate | 20 | MSPS | 8 | ||||
| Minimum Conversion Rate | 1 | MSPS | 8 | ||||
| CLK Pulse Width High | 15 | ns | DCS function not applicable for AD9245BCP-20 | 8 | |||
| CLK Pulse Width Low | 15 | ns | DCS function not applicable for AD9245BCP-20 | 8 | |||
| CLK Period | 50 | ns | 8 | ||||
| Output Delay | tPD | 3.5 | ns | 5 pF load on each output; CLK 50% to DATA 50% | 8 | ||
| Pipeline Delay (Latency) | 7 | Cycles | 8 | ||||
| Aperture Delay | tA | 1 | ns | 8 | |||
| Aperture Uncertainty Jitter | tJ | 0.5 | ps rms | 8 | |||
| Wake-Up Time | 3 | ms | 0.1 µF and 10 µF capacitors on REFT and REFB | 8 | |||
| Out-of-Range Recovery Time | 1 | Cycles | 8 | ||||
| AVDD to AGND | AVDD | -0.3 | 3.9 | V | With respect to AGND | 9 | |
| DRVDD to DGND | DRVDD | -0.3 | 3.9 | V | With respect to DGND | 9 | |
| AGND to DGND | -0.3 | 0.3 | V | 9 | |||
| AVDD to DRVDD | -3.9 | 3.9 | V | 9 | |||
| D0 to D13 | -0.3 | V | With respect to DGND; upper limit printed as DRVDD + 0.3 | 9 | |||
| CLK, MODE | -0.3 | V | With respect to AGND; upper limit printed as AVDD + 0.3 | 9 | |||
| VIN+, VIN- | -0.3 | V | With respect to AGND; upper limit printed as AVDD + 0.3 | 9 | |||
| VREF | -0.3 | V | With respect to AGND; upper limit printed as AVDD + 0.3 | 9 | |||
| SENSE | -0.3 | V | With respect to AGND; upper limit printed as AVDD + 0.3 | 9 | |||
| REFT, REFB | -0.3 | V | With respect to AGND; upper limit printed as AVDD + 0.3 | 9 | |||
| PDWN | -0.3 | V | With respect to AGND; upper limit printed as AVDD + 0.3 | 9 | |||
| Storage Temperature Range | -65 | 125 | °C | 9 | |||
| Lead Temperature | 300 | °C | Soldering 10 sec | 9 | |||
| Junction Temperature | 150 | °C | 9 | ||||
| Thermal Resistance θJA | θJA | 32.5 | °C/W | 32-Lead LFCSP; 4-layer board, still air, EIA/JESD51-1 | 9 | ||
| Thermal Resistance θJC | θJC | 32.71 | °C/W | 32-Lead LFCSP | 9 |
CAD (KiCad official)
- Symbol:
AD9245BCPZ-20 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
ad9245bcpz-20-etched.step/ad9245bcpz-20-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad9245bcpz-20.step/ad9245bcpz-20.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
8fa61d01efdba4ad, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).