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TPS54317RHFR
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Texas Instruments DC-DC Converters, VQFN-24-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownTPS54317RHFR
Texas Instruments · DC-DC Converters · VQFN-24-EP(4x5)
TPS54317RHFR from Texas Instruments, in a VQFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output; connect the compensation network from COMP to VSENSE, with absolute maximum -0.3 to 7 V and 6 mA sink current. |
| 2 | PWRGD | output | Open-drain power good output that is high when VSENSE is at or above 90% of Vref and low otherwise, and also low when SS/ENA is low or thermal shutdown is active; absolute maximum -0.3 to 7 V and 10 mA sink current. |
| 3 | BOOT | passive | Bootstrap input; connect a 0.022 µF to 0.1 µF low-ESR capacitor from BOOT to PH to generate the floating high-side driver supply, with absolute maximum -0.3 to 17 V. |
| 4 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; steady-state limit -0.6 to 10 V and transient (<20 ns) limit -2 to 10 V. |
| 5 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; steady-state limit -0.6 to 10 V and transient (<20 ns) limit -2 to 10 V. |
| 6 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; steady-state limit -0.6 to 10 V and transient (<20 ns) limit -2 to 10 V. |
| 7 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; steady-state limit -0.6 to 10 V and transient (<20 ns) limit -2 to 10 V. |
| 8 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; steady-state limit -0.6 to 10 V and transient (<20 ns) limit -2 to 10 V. |
| 9 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; steady-state limit -0.6 to 10 V and transient (<20 ns) limit -2 to 10 V. |
| 10 | NC | unconnected | Not connected internally. |
| 11 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns and capacitor negative terminals. |
| 12 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns and capacitor negative terminals. |
| 13 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns and capacitor negative terminals. |
| 14 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns and capacitor negative terminals. |
| 15 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, recommended 3 to 6 V with absolute maximum -0.3 to 7 V; bypass to PGND with a low-ESR 1 µF to 10 µF ceramic capacitor. |
| 16 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, recommended 3 to 6 V with absolute maximum -0.3 to 7 V; bypass to PGND with a low-ESR 1 µF to 10 µF ceramic capacitor. |
| 17 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, recommended 3 to 6 V with absolute maximum -0.3 to 7 V; bypass to PGND with a low-ESR 1 µF to 10 µF ceramic capacitor. |
| 18 | VBIAS | power_out | Internal bias regulator output supplying internal circuitry; bypass to AGND with a low-ESR 0.1 µF to 1.0 µF ceramic capacitor, with absolute maximum -0.3 to 7 V and 6 mA limit. |
| 19 | SS/ENA | bidirectional | Slow-start and enable pin: logic enable input (threshold 0.82 to 1.4 V, typical 1.2 V) and slow-start capacitor input that sets start-up time, with absolute maximum -0.3 to 7 V and 10 mA sink current. |
| 20 | SYNC | input | Synchronization input to lock to an external oscillator or select between two internally set switching frequencies; when synchronizing externally, a resistor must be connected to RT; absolute maximum -0.3 to 7 V. |
| 21 | NC | unconnected | Not connected internally. |
| 22 | RT | input | Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency from 280 kHz to 1.6 MHz, with absolute maximum -0.3 to 6 V. |
| 23 | AGND | power_in | Analog ground and return for the compensation network, output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin; connect directly to the AGND trace. |
| 24 | VSNS | input | Error amplifier inverting input (VSENSE); absolute maximum -0.3 to 4 V. |
| 25 | AGND | power_in | Exposed thermal pad (pin 25) that must be connected to AGND for ground and heat dissipation; use 0.013 inch diameter vias from the pad to the analog ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x5) |
| Category | Power Supply Chip |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, SS/ENA, SYNC input voltage range | VI | -0.3 | 7 | V | 2 | ||
| RT input voltage range | VI | -0.3 | 6 | V | 2 | ||
| VSENSE input voltage range | VI | -0.3 | 4 | V | 2 | ||
| BOOT input voltage range | VI | -0.3 | 17 | V | 2 | ||
| VBIAS, PWRGD, COMP input voltage range | VI | -0.3 | 7 | V | 2 | ||
| PH output voltage range, steady state | VO | -0.6 | 10 | V | steady state | 2 | |
| PH output voltage range, transient | VO | -2 | 10 | V | transient < 20 ns | 2 | |
| COMP, VBIAS output current range | IO | 6 | mA | 2 | |||
| PH output current range | IO | 6 | A | 2 | |||
| COMP sink current | 6 | mA | 2 | ||||
| SS/ENA, PWRGD sink current | 10 | mA | 2 | ||||
| Voltage differential AGND to PGND | -0.3 | 0.3 | V | 2 | |||
| Operating virtual junction temperature range | TJ | -40 | 150 | °C | 2 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| Input voltage range | VI | 3 | 6 | V | 2 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 2 | ||
| Junction-to-ambient thermal impedance, 24-pin RHF with solder | 19.7 | °C/W | Test board per note (2): 3 in x 3 in, 4 layers, 6 thermal vias | 3 | |||
| Junction-to-case thermal impedance, 24-pin RHF with solder | 1.7 | °C/W | 3 | ||||
| Input voltage range, VIN | VI | 3 | 6 | V | TJ = -40 °C to 125 °C | 3 | |
| Quiescent current | IQ | 6.2 | 9.6 | mA | fs = 350 kHz, SYNC = 0.8 V, RT open | 3 | |
| Quiescent current | IQ | 8.4 | 12.8 | mA | fs = 550 kHz, SYNC ≥ 2.5 V, RT open, phase pin open | 3 | |
| Shutdown current | IQ | 1 | 1.4 | mA | Shutdown, SS/ENA = 0 V | 3 | |
| Start threshold voltage, UVLO | 2.95 | 3 | V | 3 | |||
| Stop threshold voltage, UVLO | 2.7 | 2.8 | V | 3 | |||
| Hysteresis voltage, UVLO | 0.14 | 0.16 | V | 3 | |||
| Output voltage, VBIAS | VO | 2.7 | 2.8 | 2.9 | V | I(VBIAS) = 0 | 3 |
| Output current, VBIAS | 100 | µA | Static resistive loads only | 3 | |||
| Vref accuracy | Vref | 0.882 | 0.891 | 0.9 | V | 3 | |
| Internally set free-running frequency range | fs | 280 | 350 | 420 | kHz | SYNC ≤ 0.8 V, RT open | 3 |
| Internally set free-running frequency range | fs | 440 | 550 | 660 | kHz | SYNC ≥ 2.5 V, RT open | 3 |
| Externally set free-running frequency range | fs | 460 | 500 | 540 | kHz | RT = 100 kΩ (1% resistor to AGND) | 3 |
| Externally set free-running frequency range | fs | 995 | 1075 | 1155 | kHz | RT = 43 kΩ (1% resistor to AGND) | 3 |
| High-level threshold voltage, SYNC | 2.5 | V | 3 | ||||
| Low-level threshold voltage, SYNC | 0.8 | V | 3 | ||||
| Pulse duration, SYNC | 50 | ns | Specified by design | 3 | |||
| Frequency range, SYNC | 330 | 1600 | kHz | 3 | |||
| Minimum controllable on time | 150 | ns | 3 | ||||
| Maximum duty cycle | 90 | % | 3 | ||||
| Error amplifier open loop voltage gain | 90 | 110 | dB | 1 kΩ COMP to AGND | 4 | ||
| Error amplifier unity gain bandwidth | 3 | 5 | MHz | Parallel 10 kΩ, 160 pF COMP to AGND | 4 | ||
| Error amplifier common-mode input voltage range | 0 | V | Powered by internal LDO; upper limit is VBIAS (not numeric) | 4 | |||
| Input bias current, VSENSE | IIB | 60 | 250 | nA | VSENSE = Vref | 4 | |
| Output voltage slew rate (symmetric), VO COMP | 1 | 1.4 | V/µs | 4 | |||
| PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead time) | 70 | 85 | ns | 10 mV overdrive | 4 | ||
| Enable threshold voltage, SS/ENA | 0.82 | 1.2 | 1.4 | V | 4 | ||
| Voltage to regulate using the internal Vref, SS/ENA | 1.95 | 2.2 | V | 4 | |||
| Internal slow-start time | 2.6 | 3.35 | 4.1 | ms | 4 | ||
| Charge current, SS/ENA | 3 | 5 | 8 | µA | SS/ENA = 0 V | 4 | |
| Discharge current, SS/ENA | 1.5 | 2.3 | 4 | mA | SS/ENA = 0.2 V, VI = 2.7 V | 4 | |
| Output saturation voltage, PWRGD | 0.18 | 0.3 | V | I(sink) = 2.5 mA | 4 | ||
| Leakage current, PWRGD | 1 | µA | VI = 5.5 V | 4 | |||
| Current limit trip point | 4 | 6.5 | A | VI = 3 V, output shorted | 4 | ||
| Current limit trip point | 4.5 | 7.5 | A | VI = 6 V, output shorted | 4 | ||
| Thermal shutdown trip point | 135 | 150 | 165 | °C | 4 | ||
| Thermal shutdown hysteresis | 10 | °C | 4 | ||||
| Power MOSFET switches rDS(on) | rDS(on) | 59 | 88 | mΩ | VI = 6 V | 4 | |
| Power MOSFET switches rDS(on) | rDS(on) | 85 | 136 | mΩ | VI = 3 V | 4 |
CAD (KiCad official)
- Symbol:
TPS54317RHFR - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm - 3D model: VQFN-24-EP(4x5) (KiCad packages3D, STEP)
- 3D model files:
tps54317rhfr-etched.step/tps54317rhfr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54317rhfr.step/tps54317rhfr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
e397d8e9ee178832, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).