component

SN74F174ADR

Public Made by Adom

by adom

Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74f174adrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74F174ADR

Texas Instruments · Flip Flops · SOIC-16

SN74F174ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low asynchronous direct clear input shared by all six flip-flops; forces all Q outputs low when asserted regardless of CLK or D; requires minimum 5 ns low pulse width; VIH min 2 V, VIL max 0.8 V.
2 1Q output Registered output of flip-flop 1; updated on positive CLK edge with tPLH 2.7-8 ns and tPHL 3.4-10 ns (VCC = 5 V, CL = 50 pF); VOH min 2.5 V at IOH = -1 mA, VOL max 0.5 V at IOL = 20 mA.
3 1D input Data input of flip-flop 1; state sampled on positive CLK edge with setup time ≥4.5 ns and hold time ≥0.5 ns; VIH min 2 V, VIL max 0.8 V.
4 2D input Data input of flip-flop 2; state sampled on positive CLK edge with setup time ≥4.5 ns and hold time ≥0.5 ns; VIH min 2 V, VIL max 0.8 V.
5 2Q output Registered output of flip-flop 2; updated on positive CLK edge with tPLH 2.7-8 ns and tPHL 3.4-10 ns (VCC = 5 V, CL = 50 pF); VOH min 2.5 V at IOH = -1 mA, VOL max 0.5 V at IOL = 20 mA.
6 3D input Data input of flip-flop 3; state sampled on positive CLK edge with setup time ≥4.5 ns and hold time ≥0.5 ns; VIH min 2 V, VIL max 0.8 V.
7 3Q output Registered output of flip-flop 3; updated on positive CLK edge with tPLH 2.7-8 ns and tPHL 3.4-10 ns (VCC = 5 V, CL = 50 pF); VOH min 2.5 V at IOH = -1 mA, VOL max 0.5 V at IOL = 20 mA.
8 GND power_in Ground supply reference (0 V) for all internal TTL logic.
9 CLK input Positive-edge-triggered clock input shared by all six flip-flops; transfers D inputs to Q outputs on rising edge; max clock frequency 100 MHz at VCC = 5 V; requires CLK-high pulse ≥4 ns and CLK-low pulse ≥6 ns; VIH min 2 V, VIL max 0.8 V.
10 4Q output Registered output of flip-flop 4; updated on positive CLK edge with tPLH 2.7-8 ns and tPHL 3.4-10 ns (VCC = 5 V, CL = 50 pF); VOH min 2.5 V at IOH = -1 mA, VOL max 0.5 V at IOL = 20 mA.
11 4D input Data input of flip-flop 4; state sampled on positive CLK edge with setup time ≥4.5 ns and hold time ≥0.5 ns; VIH min 2 V, VIL max 0.8 V.
12 5Q output Registered output of flip-flop 5; updated on positive CLK edge with tPLH 2.7-8 ns and tPHL 3.4-10 ns (VCC = 5 V, CL = 50 pF); VOH min 2.5 V at IOH = -1 mA, VOL max 0.5 V at IOL = 20 mA.
13 5D input Data input of flip-flop 5; state sampled on positive CLK edge with setup time ≥4.5 ns and hold time ≥0.5 ns; VIH min 2 V, VIL max 0.8 V.
14 6D input Data input of flip-flop 6; state sampled on positive CLK edge with setup time ≥4.5 ns and hold time ≥0.5 ns; VIH min 2 V, VIL max 0.8 V.
15 6Q output Registered output of flip-flop 6; updated on positive CLK edge with tPLH 2.7-8 ns and tPHL 3.4-10 ns (VCC = 5 V, CL = 50 pF); VOH min 2.5 V at IOH = -1 mA, VOL max 0.5 V at IOL = 20 mA.
16 VCC power_in Positive TTL supply voltage; recommended operating range 4.5 V to 5.5 V (nom 5 V); absolute maximum 7 V; ICCH max 45 mA, ICCL max 55 mA at VCC = 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74F174ADR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74f174adr-etched.step / sn74f174adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f174adr.step / sn74f174adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (11 pp, sha256 36c1967402fbac7b, retrieved 2026-09-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF