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Contents

README

markdown

MCP3201T-CI

Microchip Tech · Analog To Digital Converters (ADCs) · SOIC-8

MCP3201T-CI from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Reference voltage input that sets the analog input span (IN+ can vary from IN- to VREF + IN-).
2 IN+ input Positive analog input that can vary from IN- to VREF + IN-.
3 IN- input Negative analog input that can vary ±100 mV from VSS.
4 VSS power_in Ground.
5 CS/SHDN input Chip select/shutdown input; pulled low to initiate communication, pulled high to end a conversion and enter low-power standby, and must be high between conversions.
6 DOUT output SPI serial data output that shifts out the A/D conversion result, changing on the falling edge of each clock.
7 CLK input SPI serial clock input that initiates a conversion and clocks out each bit of the conversion result.
8 VDD power_in +2.7V to 5.5V power supply.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category ADC/DAC/Data Conversion
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral Nonlinearity (MCP3201-C) INL -2 1 2 LSB MCP3201-C 3
Differential Nonlinearity DNL -1 0.5 1 LSB No missing codes over temperature 3
Offset Error -3 1.25 3 LSB 3
Gain Error -5 1.25 5 LSB 3
Conversion Time tCONV 12 clock cycles 3
Throughput Rate fSAMPLE 100 ksps VDD = VREF = 5V 3
Throughput Rate fSAMPLE 50 ksps VDD = VREF = 2.7V 3
Reference Voltage Range 0.25 V Note 2; upper limit VDD 3
Reference Current Drain 100 150 µA 3
Reference Current Drain (CS high) 0.001 3 µA CS = VDD = 5V 3
Input Voltage Range (IN-) IN- -100 100 mV VSS-100 to VSS+100 3
Analog Input Leakage Current -1 0.001 1 µA 3
High Level Input Voltage VIH 0.7 VDD 3
Low Level Input Voltage VIL 0.3 VDD 3
High Level Output Voltage VOH 4.1 V IOH = -1 mA, VDD = 4.5V 4
Low Level Output Voltage VOL 0.4 V IOL = 1 mA, VDD = 4.5V 4
Input Leakage Current ILI -10 10 µA VIN = VSS or VDD 4
Output Leakage Current ILO -10 10 µA VOUT = VSS or VDD 4
Pin Capacitance (all inputs/outputs) CIN, COUT 10 pF VDD = 5.0V (Note 1), TA = +25°C, f = 1 MHz 4
Clock Frequency fCLK 1.6 MHz VDD = 5V (Note 3) 4
Clock Frequency fCLK 0.8 MHz VDD = 2.7V (Note 3) 4
Clock High Time tHI 312 ns 4
Clock Low Time tLO 312 ns 4
CS Fall To First Rising CLK Edge tSUCS 100 ns 4
CLK Fall To Output Data Valid tDO 200 ns See Test Circuits, Figure 1-2 4
CLK Fall To Output Enable tEN 200 ns See Test Circuits, Figure 1-2 4
CS Rise To Output Disable tDIS 100 ns See Test Circuits, Figure 1-2 (Note 1) 4
CS Disable Time tCSH 625 ns 4
DOUT Rise Time tR 100 ns See Test Circuits, Figure 1-2 (Note 1) 4
DOUT Fall Time tF 100 ns See Test Circuits, Figure 1-2 4
Operating Voltage VDD 2.7 5.5 V 4
Operating Current IDD 300 400 µA VDD = 5.0V, DOUT unloaded 4
Operating Current IDD 210 µA VDD = 2.7V, DOUT unloaded 4
Standby Current IDDS 0.5 2 µA CS = VDD = 5.0V 4
Specified Temperature Range TA -40 85 °C 4
Operating Temperature Range TA -40 85 °C 4
Storage Temperature Range TA -65 150 °C 4
Storage temperature -65 150 °C 3
Ambient temp. with power applied -65 125 °C 3
ESD protection on all pins (HBM) 4 kV > 4 kV 3
Thermal Resistance, 8L-SOIC θJA 149.5 °C/W 4
Analog Input Sample Time tSAMPLE 1.5 clock cycles 3
Resolution 12 bits 3
Total Harmonic Distortion THD -82 dB VIN = 0.1V to 4.9V@1 kHz 3
Signal to Noise and Distortion SINAD 72 dB VIN = 0.1V to 4.9V@1 kHz 3
Spurious Free Dynamic Range SFDR 86 dB VIN = 0.1V to 4.9V@1 kHz 3
Switch Resistance RSS 1 kΩ See Figure 4-1 3
Sample Capacitor CSAMPLE 20 pF See Figure 4-1 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead 37

CAD (KiCad official)

  • Symbol: MCP3201T-CI
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mcp3201t-ci-etched.step / mcp3201t-ci-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp3201t-ci.step / mcp3201t-ci.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (40 pp, sha256 5b068299258ac365, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF