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BQ29312PWR

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Texas Instruments Battery Management, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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BQ29312PWR

Texas Instruments · Battery Management · TSSOP-24

BQ29312PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BAT power_in Diode protected BAT+ terminal and primary power source.
2 DSG output Push-pull output discharge FET gate drive.
3 VC1 input Sense voltage input terminal for most positive cell and balance current input for most positive cell.
4 VC2 input Sense voltage input terminal for second most positive cell, balance current input for second most positive cell and return balance current for most positive cell.
5 VC3 input Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and return balance current for second most positive cell.
6 VC4 input Sense voltage input terminal for least positive cell, balance current input for least positive cell and return balance current for third most positive cell.
7 VC5 input Sense voltage input terminal for most negative cell, return balance current for least positive cell.
8 SR1 input Current sense positive terminal when charging relative to SR2.
9 SR2 input Current sense negative terminal when discharging relative to SR2 current sense terminal.
10 WDI input Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
11 CELL output Output of scaled value of the measured cell voltage.
12 GND power_in Analog ground pin and negative pack terminal.
13 SCLK bidirectional Open-drain bidirectional serial interface clock with internal 10 kΩ pull-up to V(REG).
14 SDATA bidirectional Open-drain bidirectional serial interface data with internal 10 kΩ pull-up to V(REG).
15 GND power_in Connect to GND.
16 XALERT tri_state Open-drain output used to indicate status register changes with internal 100 kΩ pull-up to V(REG).
17 TOUT output Provides thermistor bias current.
18 REG power_out Integrated 3.3-V regulator output.
19 SLEEP input This pin is pulled up to V(REG) internally; open or high level activates Sleep mode.
20 CHG output Push-pull output charge FET gate drive.
21 ZVCHG output The ZVCHG FET drive is connected here.
22 PACK power_in PACK positive terminal and alternative power source.
23 PMS input 0-V charge configuration select pin; CHG terminal ON/OFF is determined by this pin.
24 OD tri_state NCH FET open drain output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Power Management (PMIC)
Pins 24

CAD (KiCad official)

  • Symbol: BQ29312PWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: bq29312pwr-etched.step / bq29312pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq29312pwr.step / bq29312pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 d4d1510be5e6af00, retrieved 2026-10-01, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF