component
SN74LS192DR
Public Made by Adomby adom
lingxingic Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LS192DR
lingxingic · Counters, Dividers · SOP-16
SN74LS192DR from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1 | input | Parallel data input 1, loaded into Q1 when PL is LOW. |
| 2 | Q1 | output | Flip-flop output 1; set to D1 by parallel load and forced LOW by a HIGH on MR. |
| 3 | Q0 | output | Flip-flop output 0; set to D0 by parallel load and forced LOW by a HIGH on MR. |
| 4 | CPD | input | Count-down clock input; the counter counts down on the LOW-to-HIGH transition while CPU is held HIGH. |
| 5 | CPU | input | Count-up clock input; the counter counts up on the LOW-to-HIGH transition while CPD is held HIGH. |
| 6 | Q2 | output | Flip-flop output 2; set to D2 by parallel load and forced LOW by a HIGH on MR. |
| 7 | Q3 | output | Flip-flop output 3; set to D3 by parallel load and forced LOW by a HIGH on MR. |
| 8 | GND | power_in | Ground (0V) reference for all voltages in the datasheet. |
| 9 | D3 | input | Parallel data input 3, loaded into Q3 when PL is LOW. |
| 10 | D2 | input | Parallel data input 2, loaded into Q2 when PL is LOW. |
| 11 | PL | input | Asynchronous parallel load input, active LOW; loads D0 to D3 into the counter regardless of the clock inputs. |
| 12 | TCU | output | Terminal count up (carry) output, active LOW; goes LOW at count 15 on the next HIGH-to-LOW transition of CPU. |
| 13 | TCD | output | Terminal count down (borrow) output, active LOW; goes LOW in the zero state when CPD goes LOW. |
| 14 | MR | input | Asynchronous master reset input, active HIGH; a HIGH level sets Q0 to Q3 LOW and overrides both clock inputs. |
| 15 | D0 | input | Parallel data input 0, loaded into Q0 when PL is LOW. |
| 16 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 6.0 V (typical 5.0 V) with respect to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 9 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 9 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 9 | |
| output current | IO | -25 | 25 | mA | VO= -0.5V to (VCC+0.5V) | 9 | |
| supply current | ICC | 50 | mA | 9 | |||
| ground current | IGND | -50 | mA | 9 | |||
| storage temperature | Tstg | -65 | 150 | ℃ | 9 | ||
| total power dissipation | Ptot | 500 | mW | 9 | |||
| soldering temperature | TL | 260 | ℃ | 10s, SOP/TSSOP | 9 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | 10 | |
| input voltage | VI | 0 | V | 10 | |||
| output voltage | VO | 0 | V | 10 | |||
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 10 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 10 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 10 | ||
| ambient temperature | Tamb | -40 | 125 | ℃ | 10 | ||
| HIGH-level input voltage (Tamb=25℃) | VIH | 1.5 | 1.2 | V | VCC=2.0V | 10 | |
| HIGH-level input voltage (Tamb=25℃) | VIH | 3.15 | 2.4 | V | VCC=4.5V | 10 | |
| HIGH-level input voltage (Tamb=25℃) | VIH | 4.2 | 3.2 | V | VCC=6.0V | 10 | |
| LOW-level input voltage (Tamb=25℃) | VIL | 0.8 | 0.5 | V | VCC=2.0V | 10 | |
| LOW-level input voltage (Tamb=25℃) | VIL | 2.1 | 1.35 | V | VCC=4.5V | 10 | |
| LOW-level input voltage (Tamb=25℃) | VIL | 2.8 | 1.8 | V | VCC=6.0V | 10 | |
| HIGH-level output voltage (Tamb=25℃) | VOH | 1.9 | 2 | V | VI=VIH or VIL; IO=-20uA; VCC=2.0V | 10 | |
| HIGH-level output voltage (Tamb=25℃) | VOH | 4.4 | 4.5 | V | VI=VIH or VIL; IO=-20uA; VCC=4.5V | 10 | |
| HIGH-level output voltage (Tamb=25℃) | VOH | 5.9 | 6 | V | VI=VIH or VIL; IO=-20uA; VCC=6.0V | 10 | |
| HIGH-level output voltage (Tamb=25℃) | VOH | 3.98 | 4.32 | V | VI=VIH or VIL; IO=-4mA; VCC=4.5V | 10 | |
| HIGH-level output voltage (Tamb=25℃) | VOH | 5.48 | 5.81 | V | VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 10 | |
| LOW-level output voltage (Tamb=25℃) | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO=20uA; VCC=2.0V | 10 | |
| LOW-level output voltage (Tamb=25℃) | VOL | 0.15 | 0.26 | V | VI = VIH or VIL; IO=4mA; VCC=4.5V | 10 | |
| LOW-level output voltage (Tamb=25℃) | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; IO=5.2mA; VCC=6.0V | 10 | |
| input leakage current (Tamb=25℃) | II | -1 | 1 | uA | VI=VCC or GND; VCC=6.0V | 10 | |
| supply current (Tamb=25℃) | ICC | 8 | uA | VI=VCC or GND; IO=0A; VCC=6.0V | 10 | ||
| HIGH-level input voltage (Tamb=-40 to +125℃) | VIH | 1.5 | V | VCC=2.0V | 12 | ||
| HIGH-level input voltage (Tamb=-40 to +125℃) | VIH | 3.15 | V | VCC=4.5V | 12 | ||
| HIGH-level input voltage (Tamb=-40 to +125℃) | VIH | 4.2 | V | VCC=6.0V | 12 | ||
| LOW-level input voltage (Tamb=-40 to +125℃) | VIL | 0.5 | V | VCC=2.0V | 12 | ||
| LOW-level input voltage (Tamb=-40 to +125℃) | VIL | 1.35 | V | VCC=4.5V | 12 | ||
| LOW-level input voltage (Tamb=-40 to +125℃) | VIL | 1.8 | V | VCC=6.0V | 12 | ||
| HIGH-level output voltage (Tamb=-40 to +125℃) | VOH | 1.9 | V | VI=VIH or VIL; IO=-20uA; VCC=2.0V | 12 | ||
| HIGH-level output voltage (Tamb=-40 to +125℃) | VOH | 4.4 | V | VI=VIH or VIL; IO=-20uA; VCC=4.5V | 12 | ||
| HIGH-level output voltage (Tamb=-40 to +125℃) | VOH | 5.9 | V | VI=VIH or VIL; IO=-20uA; VCC=6.0V | 12 | ||
| HIGH-level output voltage (Tamb=-40 to +125℃) | VOH | 3.7 | V | VI=VIH or VIL; IO=-4mA; VCC=4.5V | 12 | ||
| HIGH-level output voltage (Tamb=-40 to +125℃) | VOH | 5.2 | V | VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 12 | ||
| LOW-level output voltage (Tamb=-40 to +125℃) | VOL | 0.1 | V | VI = VIH or VIL; IO=20uA; VCC=2.0V | 12 | ||
| LOW-level output voltage (Tamb=-40 to +125℃) | VOL | 0.4 | V | VI = VIH or VIL; IO=4mA; VCC=4.5V | 12 | ||
| input leakage current (Tamb=-40 to +125℃) | II | -1 | 1 | uA | VI=VCC or GND; VCC=6.0V | 12 | |
| supply current (Tamb=-40 to +125℃) | ICC | 160 | uA | VI=VCC or GND; IO=0A; VCC=6.0V | 12 | ||
| maximum frequency fmax (Tamb=25℃) | fmax | 4 | 12 | MHz | CPU, CPD; see Figure 7; VCC=2.0V | 14 | |
| maximum frequency fmax (Tamb=25℃) | fmax | 20 | 36 | MHz | CPU, CPD; see Figure 7; VCC=4.5V | 14 | |
| maximum frequency fmax (Tamb=25℃) | fmax | 24 | 43 | MHz | CPU, CPD; see Figure 7; VCC=6.0V | 14 | |
| maximum frequency fmax (Tamb=-40 to +125℃) | fmax | 3 | MHz | CPU, CPD; see Figure 7; VCC=2.0V | 18 | ||
| maximum frequency fmax (Tamb=-40 to +125℃) | fmax | 13 | MHz | CPU, CPD; see Figure 7; VCC=4.5V | 18 | ||
| maximum frequency fmax (Tamb=-40 to +125℃) | fmax | 16 | MHz | CPU, CPD; see Figure 7; VCC=6.0V | 18 |
CAD (KiCad official)
- Symbol:
SN74LS192DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74ls192dr-etched.step/sn74ls192dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls192dr.step/sn74ls192dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (25 pp, sha256
2f9790fc62cae142, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).