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DS90LV049TMTX

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by Ray

Texas Instruments LVDS ICs, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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DS90LV049TMTX

Texas Instruments · LVDS ICs · TSSOP-16

DS90LV049TMTX from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RIN1- input Inverting LVDS receiver 1 input. Differential input pair (with RIN1+) accepting LVDS signals with common-mode range 0.05 V to 3 V; internal fail-safe biasing places the receiver output in a known HIGH state when inputs are floating.
2 RIN1+ input Non-inverting LVDS receiver 1 input. Differential input pair (with RIN1-) accepting LVDS signals per TIA/EIA-644-A.
3 RIN2+ input Non-inverting LVDS receiver 2 input. Differential input pair (with RIN2-) accepting LVDS signals per TIA/EIA-644-A.
4 RIN2- input Inverting LVDS receiver 2 input. Differential input pair (with RIN2+) accepting LVDS signals; internal fail-safe biasing on floating inputs.
5 DOUT2- output Inverting LVDS driver 2 output. Differential output pair (with DOUT2+) driving
6 DOUT2+ output Non-inverting LVDS driver 2 output. Differential output pair (with DOUT2-) driving a 100 Ω terminated LVDS line per TIA/EIA-644-A.
7 DOUT1+ output Non-inverting LVDS driver 1 output. Differential output pair (with DOUT1-) driving a 100 Ω terminated LVDS line.
8 DOUT1- output Inverting LVDS driver 1 output. Differential output pair (with DOUT1+); TRI-STATE when disabled via EN/EN pins.
9 EN_N input Active-low enable input (EN-bar), LVCMOS levels. ANDed with EN to control TRI-STATE of all four channels (both drivers and receivers); outputs are enabled only when EN = H and EN_N = L or Open. Input high 2.0 V min, input low 0.8 V max.
10 DIN1 input LVCMOS driver 1 input. Drives LVDS driver 1 outputs (DOUT1+/-). VIH ≥ 2.0 V, VIL ≤ 0.8 V; input clamp voltage -0.6 V typ at ICL = -18 mA.
11 DIN2 input LVCMOS driver 2 input. Drives LVDS driver 2 outputs (DOUT2+/-). LVCMOS input levels: VIH ≥ 2.0 V, VIL ≤ 0.8 V.
12 VDD power_in Positive supply. +3.3 V ±10% (3.0 V min, 3.6 V max). Typical supply current IDD = 21 mA (35 mA max) enabled; 15 mA typ (25 mA max) in TRI-STATE.
13 GND power_in Ground reference (0 V) for all supply and signal levels.
14 ROUT2 output LVCMOS receiver 2 output. 3 V CMOS level output; VOH ≥ 2.7 V at IOH = -0.4 mA, VOL ≤ 0.25 V at IOL = 2 mA. TRI-STATE when disabled.
15 ROUT1 output LVCMOS receiver 1 output. 3 V CMOS level output; VOH ≥ 2.7 V, VOL ≤ 0.25 V. TRI-STATE when disabled via EN/EN_N.
16 EN input Active-high enable input, LVCMOS levels. ANDed with EN_N to control TRI-STATE of all four channels; outputs enabled only when EN = H and EN_N = L or Open (see Truth Table). VIH ≥ 2.0 V, VIL ≤ 0.8 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Interface
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • DS90LV049TMTX

CAD (KiCad official)

  • Symbol: DS90LV049TMTX
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 be164a28655a6a5d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF