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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS1296IPAG

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS1296IPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN8N	input	Differential analog negative input 8, used on ADS1298 only; connect to AVDD if unused.
2	IN8P	input	Differential analog positive input 8, used on ADS1298 only; connect to AVDD if unused.
3	IN7N	input	Differential analog negative input 7, used on ADS1298 only; connect to AVDD if unused.
4	IN7P	input	Differential analog positive input 7, used on ADS1298 only; connect to AVDD if unused.
5	IN6N	input	Differential analog negative input 6, present on ADS1296 and ADS1298; connect to AVDD if unused.
6	IN6P	input	Differential analog positive input 6, present on ADS1296 and ADS1298; connect to AVDD if unused.
7	IN5N	input	Differential analog negative input 5, present on ADS1296 and ADS1298; connect to AVDD if unused.
8	IN5P	input	Differential analog positive input 5, present on ADS1296 and ADS1298; connect to AVDD if unused.
9	IN4N	input	Differential analog negative input 4; connect to AVDD if unused.
10	IN4P	input	Differential analog positive input 4; connect to AVDD if unused.
11	IN3N	input	Differential analog negative input 3; connect to AVDD if unused.
12	IN3P	input	Differential analog positive input 3; connect to AVDD if unused.
13	IN2N	input	Differential analog negative input 2; connect to AVDD if unused.
14	IN2P	input	Differential analog positive input 2; connect to AVDD if unused.
15	IN1N	input	Differential analog negative input 1; connect to AVDD if unused.
16	IN1P	input	Differential analog positive input 1; connect to AVDD if unused.
17	TESTP_PACE_OUT1	bidirectional	Internal test signal or single-ended buffered pace output (selected by register); also usable as an auxiliary differential input when hardware pace detection is not used.
18	TESTN_PACE_OUT2	bidirectional	Internal test signal or single-ended buffered pace output (selected by register); also usable as an auxiliary differential input when hardware pace detection is not used.
19	AVDD	power_in	Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
20	AVSS	power_in	Analog ground.
21	AVDD	power_in	Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
22	AVDD	power_in	Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
23	AVSS	power_in	Analog ground.
24	VREFP	bidirectional	Positive reference voltage input/output; VREFP minus AVSS is limited to 2.5 V minimum to AVDD + 0.3 V and VREF is 2.4 V or 4 V depending on supply.
25	VREFN	input	Negative reference voltage input; tie to AVSS when the internal reference is used.
26	VCAP4	passive	Analog bypass capacitor node; connect a 1 µF capacitor to AVSS.
27	NC	unconnected	No connection; may be tied to AVDD or AVSS through a 10 kΩ resistor.
28	VCAP1	passive	Analog bypass capacitor node; connect a 22 µF capacitor to AVSS.
29	NC	unconnected	No connection; may be tied to AVDD or AVSS through a 10 kΩ resistor.
30	VCAP2	passive	Analog bypass capacitor node; connect a 1 µF capacitor to AVSS.
31	RESV1	input	Reserved for future use; must be connected to logic low (DGND).
32	AVSS	power_in	Analog ground.
33	DGND	power_in	Digital ground.
34	DIN	input	SPI data input.
35	PWDN	input	Power-down pin, active low; pulling low powers down all on-chip circuitry.
36	RESET	input	System reset pin, active low; minimum low pulse width per timing specification.
37	CLK	bidirectional	External master clock input or internal clock output (output when CLKSEL = 1 and CLK_EN = 1; tri-state otherwise); external clock 1.94 to 2.25 MHz with CLKSEL = 0.
38	START	input	Start conversion input; holding high starts continuous conversions.
39	CS	input	SPI chip select, active low; must remain low during the full serial transaction.
40	SCLK	input	SPI serial clock with Schmitt-trigger input.
41	DAISY_IN	input	Daisy-chain data input; tie to DGND if not used.
42	GPIO1	bidirectional	General-purpose digital I/O 1; must be driven when configured as input, and can serve as PACE_IN.
43	DOUT	output	SPI data output; high impedance when CS is high.
44	GPIO2	bidirectional	General-purpose digital I/O 2; must be driven when configured as input.
45	GPIO3	bidirectional	General-purpose digital I/O 3; must be driven when configured as input.
46	GPIO4	bidirectional	General-purpose digital I/O 4; must be driven when configured as input.
47	DRDY	output	Data ready output, active low; goes low when new conversion data is available.
48	DVDD	power_in	Digital power supply; DVDD must be 1.65 V to 3.6 V.
49	DGND	power_in	Digital ground.
50	DVDD	power_in	Digital power supply; DVDD must be 1.65 V to 3.6 V.
51	DGND	power_in	Digital ground.
52	CLKSEL	input	Master clock select: 0 selects external clock input, 1 selects internal oscillator.
53	AVSS1	power_in	Analog ground for the charge pump; wire in star configuration to AVSS.
54	AVDD1	power_in	Analog power supply for the charge pump; wire in star configuration to AVDD.
55	VCAP3	passive	Internally generated AVDD + 1.9 V bypass node; connect a 1 µF capacitor to AVSS.
56	AVDD	power_in	Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
57	AVSS	power_in	Analog ground.
58	AVSS	power_in	Analog ground.
59	AVDD	power_in	Analog power supply; AVDD minus AVSS must be 2.7 V to 5.25 V.
60	RLDREF	input	Right-leg drive non-inverting input reference; can be set internally to (AVDD + AVSS)/2 or driven externally.
61	RLDINV	bidirectional	Right-leg drive inverting input, analog input/output.
62	RLDIN	input	Analog input to the input multiplexer for routing the right-leg drive signal; connect to AVDD if unused.
63	RLDOUT	output	Right-leg drive analog output.
64	WCT	output	Wilson central terminal analog output; has limited drive strength and should be buffered for low-impedance loads.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-64(10x10)
Category	Data Acquisition
Pins	64

CAD (KiCad official)

Symbol: ADS1296IPAG
Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ads1296ipag-etched.step / ads1296ipag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1296ipag.step / ads1296ipag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (113 pp, sha256 a8830f56bfd11d1b, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF