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U74HC595AG-S16-R
Public Made by Adomby adom
UTC Unisonic Tech Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownU74HC595AG-S16-R
UTC Unisonic Tech · Shift Registers · SOP-16
U74HC595AG-S16-R from UTC Unisonic Tech, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Parallel 3-state latched output B of the 8-bit register, high-impedance when OE is high. |
| 2 | QC | tri_state | Parallel 3-state latched output C of the 8-bit register, high-impedance when OE is high. |
| 3 | QD | tri_state | Parallel 3-state latched output D of the 8-bit register, high-impedance when OE is high. |
| 4 | QE | tri_state | Parallel 3-state latched output E of the 8-bit register, high-impedance when OE is high. |
| 5 | QF | tri_state | Parallel 3-state latched output F of the 8-bit register, high-impedance when OE is high. |
| 6 | QG | tri_state | Parallel 3-state latched output G of the 8-bit register, high-impedance when OE is high. |
| 7 | QH | tri_state | Parallel 3-state latched output H of the 8-bit register, high-impedance when OE is high. |
| 8 | GND | power_in | Ground, 0 V reference. |
| 9 | QH' | output | Serial output of the shift register (stage H), which shifts data out on each SRCLK low-to-high transition. |
| 10 | SRCLR | input | Active-low asynchronous shift register clear input; a low level clears only the shift register. |
| 11 | SRCLK | input | Shift clock input; SER is shifted into the shift register on each low-to-high transition. |
| 12 | RCLK | input | Latch clock input; shift register data is latched to the storage register on the low-to-high transition. |
| 13 | OE | input | Active-low output enable input; high places parallel outputs QA-QH in the high-impedance state. |
| 14 | SER | input | Serial data input shifted into the internal shift register on each SRCLK low-to-high transition. |
| 15 | QA | tri_state | Parallel 3-state latched output A of the 8-bit register, high-impedance when OE is high. |
| 16 | VCC | power_in | Positive supply voltage, recommended 2 V to 6 V (absolute maximum -0.5 to 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UTC Unisonic Tech |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Supply Voltage | VCC | 2 | 6 | V | 4 | ||
| Input Voltage | VIN | 0 | V | 4 | |||
| Output Voltage | VOUT | 0 | V | 4 | |||
| Input Transition Rise or Fall Rate | ∆t/∆v | 1000 | ns | VCC=2V | 4 | ||
| Input Transition Rise or Fall Rate | ∆t/∆v | 500 | ns | VCC=4.5V | 4 | ||
| Input Transition Rise or Fall Rate | ∆t/∆v | 400 | ns | VCC=6V | 4 | ||
| Supply Voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input Clamp Current | IIK | -20 | 20 | mA | VIN <0 | 4 | |
| Output Clamp Current | IOK | -20 | 20 | mA | VOUT <0 | 4 | |
| Output Current | IOUT | -35 | 35 | mA | 4 | ||
| VCC or GND Current | ICC | -75 | 75 | mA | 4 | ||
| Power Dissipation | PD | 500 | mW | SOP-16 package | 4 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC=2V | 5 | ||
| HIGH-level input voltage | VIH | 2.1 | V | VCC=3V | 5 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC=4.5V | 5 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC=6V | 5 | ||
| LOW-level input voltage (printed as LOW-lever output voltage) | VIL | 0.5 | V | VCC=2V | 5 | ||
| LOW-level input voltage (printed as LOW-lever output voltage) | VIL | 0.9 | V | VCC=3V | 5 | ||
| LOW-level input voltage (printed as LOW-lever output voltage) | VIL | 1.35 | V | VCC=4.5V | 5 | ||
| LOW-level input voltage (printed as LOW-lever output voltage) | VIL | 1.8 | V | VCC=6V | 5 | ||
| High-Level Output Voltage, QA-QH | VOH | 1.9 | 2 | V | VCC=2V, IOH=-20μA | 5 | |
| High-Level Output Voltage, QA-QH | VOH | 4.4 | 4.5 | V | VCC=4.5V, IOH=-20μA | 5 | |
| High-Level Output Voltage, QA-QH | VOH | 5.9 | 6 | V | VCC=6V, IOH=-20μA | 5 | |
| High-Level Output Voltage, QA-QH | VOH | 2.48 | V | VCC=3V, IOH=-2.4mA | 5 | ||
| High-Level Output Voltage, QA-QH | VOH | 3.98 | V | VCC=4.5V, IOH=-6mA | 5 | ||
| High-Level Output Voltage, QA-QH | VOH | 5.48 | V | VCC=6V, IOH=-7.8mA | 5 | ||
| Low-Level Output Voltage, QA-QH | VOL | 0.002 | 0.1 | V | VCC=2V, IOL=20μA | 5 | |
| Low-Level Output Voltage, QA-QH | VOL | 0.001 | 0.1 | V | VCC=4.5V, IOL=20μA | 5 | |
| Low-Level Output Voltage, QA-QH | VOL | 0.26 | V | VCC=3V, IOL=2.4mA | 5 | ||
| High-Level Output Voltage, QH | VOH | 1.9 | 2 | V | VCC=2V, IOH=-20μA | 5 | |
| High-Level Output Voltage, QH | VOH | 4.4 | 4.5 | V | VCC=4.5V, IOH=-20μA | 5 | |
| High-Level Output Voltage, QH | VOH | 5.9 | 6 | V | VCC=6V, IOH=-20μA | 5 | |
| High-Level Output Voltage, QH | VOH | 2.48 | V | VCC=3V, IOH=-2.4mA | 5 | ||
| High-Level Output Voltage, QH | VOH | 3.98 | V | VCC=4.5V, IOH=-4mA | 5 | ||
| High-Level Output Voltage, QH | VOH | 5.48 | V | VCC=6V, IOH=-5.2mA | 5 | ||
| Low-Level Output Voltage, QH | VOL | 0.002 | 0.1 | V | VCC=2V, IOL=20μA | 5 | |
| Low-Level Output Voltage, QH | VOL | 0.001 | 0.1 | V | VCC=4.5V, IOL=20μA | 5 | |
| Low-Level Output Voltage, QH | VOL | 0.26 | V | VCC=3V, IOL=2.4mA | 5 | ||
| Input Leakage Current | II(LEAK) | -0.1 | 0.1 | μA | VCC=6V, VIN=VCC or GND | 5 | |
| Output OFF-state current | IOZ | -0.5 | 0.5 | μA | VCC=6V, VOUT=VCC or GND | 5 | |
| Quiescent Supply Current | ICC | 4 | μA | VCC=6V, VIN=VCC or GND, IOUT=0 | 5 | ||
| Input Capacitance | CIN | 10 | pF | VCC=6V, VIN=VCC or GND | 5 | ||
| Maximum clock pulse frequency | fmax | 6 | 26 | MHz | CL=50pF, VCC=2V | 6 | |
| Maximum clock pulse frequency | fmax | 30 | 38 | MHz | CL=50pF, VCC=4.5V | 6 | |
| Maximum clock pulse frequency | fmax | 35 | 42 | MHz | CL=50pF, VCC=6V | 6 | |
| Propagation delay from input (SRCLK) to output (QH') | 50 | 140 | ns | CL=50pF, VCC=2V | 6 | ||
| Propagation delay from input (SRCLK) to output (QH') | 17 | 28 | ns | CL=50pF, VCC=4.5V | 6 | ||
| Propagation delay from input (SRCLK) to output (QH') | 14 | 24 | ns | CL=50pF, VCC=6V | 6 | ||
| Propagation delay from input (RCLK) to output (QA-QH) | tPD | 60 | 200 | ns | CL=150pF, VCC=2V | 6 | |
| Propagation delay from input (RCLK) to output (QA-QH) | tPD | 22 | 40 | ns | CL=150pF, VCC=4.5V | 6 | |
| Propagation delay from input (RCLK) to output (QA-QH) | tPD | 19 | 34 | ns | CL=150pF, VCC=6V | 6 |
CAD (KiCad official)
- Symbol:
U74HC595AG-S16-R - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
u74hc595ag-s16-r-etched.step/u74hc595ag-s16-r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);u74hc595ag-s16-r.step/u74hc595ag-s16-r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UTC Unisonic Tech datasheet (8 pp, sha256
9e447896ac8d20fd, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).