component
AP7366-12W5-7
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Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-25. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAP7366-12W5-7
Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-25
AP7366-12W5-7 from Diodes Incorporated, in a SOT-25. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Voltage input pin (2.2V to 6V operating range); bypass to ground through at least a 1µF MLCC capacitor. |
| 2 | GND | power_in | Ground. |
| 3 | EN | input | Active-high enable input; logic-high at or above 1.0V turns the device on, logic-low at or below 0.3V turns it off, and it can be tied to IN if unused. |
| 4 | NC | unconnected | No connection on the fixed-output SOT25 version. |
| 5 | OUT | power_out | Voltage output pin (1.2V fixed for this part); bypass to ground through a 1µF MLCC capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-25 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy (1.0V ≦ VOUT < 1.5V) | VOUT | -0.015 | 0.015 | V | IOUT = 10mA; printed VOUT - 0.015 to VOUT + 0.015 (offset from nominal 1.2V) | 4 | |
| Input Quiescent Current | IQ | 60 | 80 | μA | VEN = VIN, IOUT = 0mA | 4 | |
| Input Shutdown Current | ISHDN | -1 | 0.05 | 1 | μA | VEN = 0V, IOUT = 0mA | 4 |
| Line Regulation | ΔVOUT/ΔVIN/VOUT | 0.01 | 0.1 | %/V | VIN = (VOUT +1V) to 5.5V, IOUT = 10mA, TA = +25°C | 4 | |
| Line Regulation over temperature | ΔVOUT/ΔVIN/VOUT | 0.2 | %/V | VIN = (VOUT +1V) to 5.5V, IOUT = 10mA, -40°C ≦ TA ≦ +85°C | 4 | ||
| Load Regulation | ΔVOUT/VOUT | -1.5 | 1.5 | % | IOUT = 1mA to 600mA, 1.0V ≦ VOUT ≦ 1.2V | 4 | |
| Dropout Voltage | VDROPOUT | 480 | 700 | mV | VOUT = 1.2V, IOUT = 300mA | 4 | |
| Dropout Voltage | VDROPOUT | 800 | 1000 | mV | VOUT = 1.2V, IOUT = 600mA | 4 | |
| Current Limit | ILIMIT | 0.66 | 1 | A | VIN = VOUT + 1V | 4 | |
| EN Input Logic-Low Voltage | VIL | 0.3 | V | VIN = VIN-Min to VIN-Max | 4 | ||
| EN Input Logic-High Voltage | VIH | 1 | V | VIN = VIN-Min to VIN-Max (max VIN) | 4 | ||
| EN Input Leakage Current | IEN | -0.1 | 0.1 | μA | VIN = 5.5V or VEN = 0V | 4 | |
| Input Voltage (abs max) | VIN | 6.5 | V | 3 | |||
| ESD HBM | ESD HBM | 2000 | V | Human Body Model | 3 | ||
| ESD CDM | ESD CDM | -1000 | 1000 | V | Charged Device Model | 3 | |
| Storage Temperature Range | TST | -65 | 150 | °C | 3 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| Input Voltage | VIN | 2.2 | 6 | V | 3 | ||
| Output Voltage | VOUT | 0.8 | 5 | V | 3 | ||
| Output Current | IOUT | 0 | 600 | mA | 3 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| PSRR | PSRR | 75 | dB | f = 1kHz, IOUT = 100mA | 4 | ||
| PSRR | PSRR | 55 | dB | f = 10kHz, IOUT = 100mA | 4 | ||
| Short-Circuit Current | ISHORT | 250 | mA | VIN = VOUT + 1V, Output Voltage <15% of VOUT | 4 | ||
| Start-Up Time | tST | 150 | μs | VOUT = 0V to 3.0V, RL = 30Ω | 4 | ||
| Thermal Shutdown Threshold | TSHDN | 150 | °C | 4 | |||
| Thermal Shutdown Hysteresis | THYS | 20 | °C | 4 | |||
| EN Pulldown Resistor | RENPD | 3 | MΩ | 5 | |||
| Output Discharge Resistor | RPD | 100 | Ω | VOL = 1V | 5 | ||
| Output Voltage Temperature Coefficient | ΔVOUT/ΔTA/VOUT | 100 | ppm/°C | IOUT = 100mA, -40°C ≤ TA ≤ +85°C (printed ±100) | 5 | ||
| Thermal Resistance Junction-to-Ambient | θJA | 169 | °C/W | SOT25, FR-4, 1oz copper, minimum recommended pad layout | 5 | ||
| Thermal Resistance Junction-to-Case | θJC | 31 | °C/W | SOT25, FR-4, 1oz copper, minimum recommended pad layout | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | reduce noise. For PCB layout, a wide copper trace is required for both IN and GND pins. A lower ESR capacitor type allows the use of less | 8 |
CAD (KiCad official)
- Symbol:
AP7366-12W5-7 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-25 (KiCad packages3D, STEP)
- 3D model files:
ap7366-12w5-7-etched.step/ap7366-12w5-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ap7366-12w5-7.step/ap7366-12w5-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (15 pp, sha256
e18fe72219e65037, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).