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SI5340B-D-GM

Public Made by Adom

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Skyworks Solutions Clock Generators / Frequency Synthesizers / PLL, QFN-44(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipsi5340b-d-gmfactory-2.0.0extractor-text

Verified SI5340B-D-GM

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 45 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SI5340B-D-GM · QFN-44(7x7) · 45 pins
  • ✓copper: 45 copper pads, none touching another net
  • ✓datasheet: all 45 pin names found in the 49-page datasheet
  • ✓distributor: lcsc C3607873, digikey SI5340B-D-GM-ND, mouser 634-SI5340B-D-GM
  • ✓family: QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-80cjx2iz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.43)
  • ✓pads: 45 pins = 45 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 45 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ si5340b-d-gm.kicad_sym✓ si5340b-d-gm.kicad_mod✓ si5340b-d-gm.step
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Contents

README

markdown

SI5340B-D-GM

Skyworks Solutions · Clock Generators / Frequency Synthesizers / PLL · QFN-44(7x7)

SI5340B-D-GM from Skyworks Solutions, in a QFN-44(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 input Clock input that accepts differential or single-ended clock signals; it is high-impedance and must be terminated externally.
2 IN1b input Complementary half of the IN1 clock input pair, accepting differential or single-ended clocks; it is high-impedance and must be terminated externally.
3 IN_SEL0 input Input reference select bit 0 used in manual pin-controlled mode to choose the active clock input; internally pulled up with a ~20 kΩ resistor to the IO_VDD_SEL voltage and can be left unconnected.
4 X1 passive XTAL shield pin that must be connected directly to the XTAL ground pins, must not be tied to the PCB ground plane, and should be left disconnected when XA/XB is driven by an external reference clock.
5 XA input Crystal or external clock input, selected when IN_SEL[1:0] = 11b; if unused and powered down it can be left unconnected.
6 XB input Complementary crystal or external clock input for XA, used under the same conditions and may be left unconnected if unused and powered down.
7 X2 passive XTAL shield pin with the same requirements as X1: connect directly to the XTAL ground pins, keep off the PCB ground plane, and leave disconnected when using an external reference clock.
8 VDDA power_in Core supply voltage of 3.3 V that requires a 3.3 V power source, with a 1.0 µF bypass capacitor recommended.
9 VDDA power_in Core supply voltage of 3.3 V that requires a 3.3 V power source, with a 1.0 µF bypass capacitor recommended.
10 IN2 input Clock input that accepts differential or single-ended clock signals; it is high-impedance and must be terminated externally.
11 IN2b input Complementary half of the IN2 clock input pair, accepting differential or single-ended clocks; it is high-impedance and must be terminated externally.
12 OEb input Output enable that disables all outputs when held high; it is internally pulled low and can be left unconnected when not in use.
13 SDA/SDIO bidirectional Serial data pin: SDA in I2C mode (requires an external pull-up of at least 1 kΩ), bidirectional SDIO in 3-wire SPI, or SDI in 4-wire SPI; no pull-up is needed in SPI mode.
14 SCLK input Serial clock input for I2C and SPI modes, internally pulled up with ~20 kΩ to the IO_VDD_SEL voltage, and requiring an external pull-up of at least 1 kΩ in I2C mode.
15 A1/SDO bidirectional Address select A1 in I2C mode (no internal pull-up or pull-down) or serial data output SDO in 4-wire SPI mode, driving high to the IO_VDD_SEL-selected voltage.
16 A0/CSb input Hardware address A0 in I2C mode or active-low chip select in SPI mode, internally pulled up with ~20 kΩ to the IO_VDD_SEL-selected voltage.
17 RSTb input Active-low device reset that performs power-on reset and forces registers to defaults; clock outputs are disabled during reset and the pin is internally pulled up with ~20 kΩ.
18 VDDO0 power_in Output clock supply for OUT0 driver at 3.3 V, 2.5 V or 1.8 V; leave unconnected if the output driver is unused.
19 OUT0b output Complementary output clock 0 with register-configurable output format; termination per 3.5.2 and 3.5.4, and left unconnected if unused.
20 OUT0 output Output clock 0 with programmable signal amplitude when configured as differential, format set by register control; left unconnected if unused.
21 VDD power_in Core supply voltage of 1.8 V, with a 1.0 µF bypass capacitor recommended.
22 NC unconnected No connect pin not connected to the die; leave disconnected.
23 VDDO1 power_in Output clock supply for OUT1 driver at 3.3 V, 2.5 V or 1.8 V; leave unconnected if the output driver is unused.
24 OUT1b output Complementary output clock 1 with register-configurable output format; left unconnected if unused.
25 OUT1 output Output clock 1 with programmable signal amplitude when configured as differential; left unconnected if unused.
26 VDDS power_in Status output supply that sets the VOL/VOH of the LOLb and LOS_XAXBb outputs; a 0.1 µF to 1.0 µF bypass capacitor is recommended.
27 LOLb output Loss-of-lock output that is high when the DSPLL is locked and low when out of lock; no external pull-up or pull-down is needed.
28 LOS_XAXBb output Loss-of-signal output that indicates a loss of signal at the XA/XB pins.
29 VDDO2 power_in Output clock supply for OUT2 driver at 3.3 V, 2.5 V or 1.8 V; leave unconnected if the output driver is unused.
30 OUT2b output Complementary output clock 2 with register-configurable output format; left unconnected if unused.
31 OUT2 output Output clock 2 with programmable signal amplitude when configured as differential; left unconnected if unused.
32 VDD power_in Core supply voltage of 1.8 V, with a 1.0 µF bypass capacitor recommended.
33 INTRb output Interrupt output asserted low on a device status change; it is push-pull and should be left unconnected when not in use.
34 VDDO3 power_in Output clock supply for OUT3 driver at 3.3 V, 2.5 V or 1.8 V; leave unconnected if the output driver is unused.
35 OUT3b output Complementary output clock 3 with register-configurable output format; left unconnected if unused.
36 OUT3 output Output clock 3 with programmable signal amplitude when configured as differential; left unconnected if unused.
37 IN_SEL1 input Input reference select bit 1 used in manual pin-controlled mode with IN_SEL0; internally pulled up with ~20 kΩ and can be left unconnected.
38 I2C_SEL input Serial interface select: high selects I2C mode and low selects SPI mode; internally pulled up with ~20 kΩ to the IO_VDD_SEL-selected voltage.
39 VDD power_in Core supply voltage of 1.8 V, with a 1.0 µF bypass capacitor recommended.
40 VDD power_in Core supply voltage of 1.8 V, with a 1.0 µF bypass capacitor recommended.
41 FB_IN input External feedback input for optional zero delay mode; if unused and powered down it can be left floating.
42 FB_INb input Complementary external feedback input for zero delay mode; if unused and powered down it can be left floating.
43 IN0 input Clock input that accepts differential or single-ended clock signals; it is high-impedance and must be terminated externally.
44 IN0b input Complementary half of the IN0 clock input pair, accepting differential or single-ended clocks; it is high-impedance and must be terminated externally.
45 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Skyworks Solutions
Package QFN-44(7x7)
Category RTC/Clock Chip
Pins 45

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Temperature TA -40 25 85 °C 17
Junction Temperature TJMAX 125 °C 17
Core Supply Voltage VDD 1.71 1.8 1.89 V 17
Core Supply Voltage (3.3 V) VDDA 3.14 3.3 3.47 V 17
Output Driver Supply Voltage VDDO 3.14 3.3 3.47 V 17
Output Driver Supply Voltage VDDO 2.37 2.5 2.62 V 17
Output Driver Supply Voltage VDDO 1.71 1.8 1.89 V 17
Core Supply Current IDD 115 230 mA Si5340/41; Si5340 test config: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz 18
Core Supply Current (analog) IDDA 120 130 mA Si5340/41 18
Output Buffer Supply Current, LVPECL Output IDDOx 22 26 mA LVPECL output @ 156.25 MHz 18
Output Buffer Supply Current, LVDS Output IDDOx 15 18 mA LVDS output @ 156.25 MHz 18
Output Buffer Supply Current, 3.3 V LVCMOS Output IDDOx 22 30 mA 3.3 V LVCMOS output @ 156.25 MHz 18
Output Buffer Supply Current, 2.5 V LVCMOS Output IDDOx 18 23 mA 2.5 V LVCMOS output @ 156.25 MHz 18
Output Buffer Supply Current, 1.8 V LVCMOS Output IDDOx 12 16 mA 1.8 V LVCMOS output @ 156.25 MHz 18
Total Power Dissipation Pd 680 875 mW Si5340; Si5340 test config: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz 18
Input Frequency Range, differential fIN 10 750 MHz Differential 19
Input Frequency Range, all single-ended signals (including LVCMOS) fIN 10 250 MHz All single-ended signals (including LVCMOS) 19
Input Voltage Swing, differential AC-coupled VIN 100 1800 mVpp_se Differential AC-coupled, fIN < 250 MHz 19
Input Voltage Swing, differential AC-coupled VIN 225 1800 mVpp_se Differential AC-coupled, 250 MHz < fIN < 750 MHz 19
Input Voltage Swing, single-ended AC-coupled VIN 100 3600 mVpp_se Single-ended AC-coupled, fIN < 250 MHz 19
Slew Rate (standard input buffer) SR 400 V/μs 19
Input Frequency (pulsed CMOS input buffer, DC coupled) fIN 10 250 MHz Pulsed CMOS input buffer - DC coupled (IN0, IN1, IN2) 19
Input Voltage VIL (pulsed CMOS input buffer) VIL -0.2 0.4 V Pulsed CMOS input buffer - DC coupled (IN0, IN1, IN2) 19
Input Voltage VIH (pulsed CMOS input buffer) VIH 0.8 V Pulsed CMOS input buffer - DC coupled (IN0, IN1, IN2) 19
Minimum Pulse Width PW 1.6 ns Pulse input (pulsed CMOS input buffer) 19
Input Frequency Range, REFCLK (full operating range) fIN 10 200 MHz Full operating range; jitter performance may be reduced 19
Input Frequency Range, REFCLK (range for best jitter) fIN 48 54 MHz Range for best jitter 19
Input Single-ended Voltage Swing (REFCLK) VIN_SE 365 2000 mVpp_se 19
Input Differential Voltage Swing (REFCLK) VIN_DIFF 365 2500 mVpp_diff 19
Slew Rate (REFCLK) SR 400 V/μs Imposed for best jitter performance 19
Input Duty Cycle (REFCLK) DC 40 60 % 19
Minimum Pulse Width (RSTb) TPW 100 ns RSTb only 20
Initial Start-Up Time tSTART 30 45 ms Time from power-up to when the device generates clocks (input frequency >48 MHz) 24
PLL Lock Time tACQ 15 150 ms fIN = 19.44 MHz 24
POR to Serial Interface Ready tRDY 15 ms 24
Jitter Generation, locked to external clock JGEN 140 180 fs rms Integer mode; 12 kHz to 20 MHz 25
Jitter Generation, locked to external clock JGEN 160 210 fs rms Fractional/DCO mode; 12 kHz to 20 MHz 25
Jitter Generation, locked to external XTAL (48 MHz) JGEN 90 140 fs rms Integer mode; 12 kHz to 20 MHz 25
Jitter Generation, locked to external XTAL (48 MHz) JGEN 115 170 fs rms Fractional/DCO mode; 12 kHz to 20 MHz 25
Crystal Frequency Range fXTAL 24.97 54.06 MHz Full operating range; jitter performance may be reduced 30
Crystal Frequency Range (best jitter) fXTAL 48 54 MHz Range for best jitter 30
Crystal Drive Level dL 200 μW 30
SCLK Frequency (3-wire SPI) fSPI 20 MHz 29
SCLK Duty Cycle (3-wire SPI) TDC 40 60 % 29
SCLK Period (3-wire SPI) TC 50 ns 29
Delay Time, SCLK Fall to SDO Turn-on (3-wire SPI) TD1 12.5 20 ns 29
Setup Time, CSb to SCLK (3-wire SPI) TSU1 5 ns 29
Hold Time, SCLK Fall to CSb (3-wire SPI) TH1 5 ns 29
Storage Temperature Range TSTG -55 150 °C 31
DC Supply Voltage (VDD) VDD -0.5 3.8 V 31
DC Supply Voltage (VDDA) VDDA -0.5 3.8 V 31
DC Supply Voltage (VDDO) VDDO -0.5 3.8 V 31
Input Voltage Range (IN0-IN2, FB_IN) VI1 -1 3.8 V 31
Input Voltage Range (IN_SEL[1:0], RSTb, OEb, SYNCb, I2C_SEL, SDI, SCLK, A0/CSb, A1, SDA/SDIO, FINC/FDEC) VI2 -0.5 3.8 V 31
Input Voltage Range (XA/XB) VI3 -0.5 2.7 V 31
Maximum Junction Temperature in Operation TJCT 125 °C 31
ESD Tolerance 2 kV HBM, 100 pF, 1.5 kΩ 31
Soldering Temperature (peak) TPEAK 260 °C Pb-free profile 31
Thermal Resistance, Junction to Ambient ϴJA 22.3 °C/W Still air 30
Thermal Resistance, Junction to Case ϴJC 10.9 °C/W 30

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 42

CAD (KiCad official)

  • Symbol: SI5340B-D-GM
  • Footprint: Package_DFN_QFN:QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-44(7x7) (KiCad packages3D, STEP)
  • 3D model files: si5340b-d-gm-etched.step / si5340b-d-gm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si5340b-d-gm.step / si5340b-d-gm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Skyworks Solutions datasheet (49 pp, sha256 a3f57dfa26cfac63, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF