component
LESD8D5.0CN3T6G
Public Made by Adomby adom
LRC ESD And Surge Protection (TVS/ESD), SOT-883. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLESD8D5.0CN3T6G
LRC · ESD And Surge Protection (TVS/ESD) · SOT-883
LESD8D5.0CN3T6G from LRC, in a SOT-883. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O 1 | passive | Protected line 1, connected through a bidirectional TVS diode (VRWM 5.0 V, VBR 5.6 V min at 1 mA) to common pin 3. |
| 2 | I/O 2 | passive | Protected line 2, connected through a bidirectional TVS diode (VRWM 5.0 V, VBR 5.6 V min at 1 mA) to common pin 3. |
| 3 | COMMON | passive | Common node of both TVS diodes, typically tied to ground as the shared return for the ESD clamp (±25 kV air, ±20 kV contact per IEC 61000-4-2). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-883 |
| Category | Circuit Protection |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Reverse Peak Pulse Current | IPP | 5.5 | A | (Note 3) surge current per Figure 3 | 2 | ||
| Clamping Voltage @ maximum IPP | VC | 12.5 | V | @ MAX IPP (Note 3) | 2 | ||
| Clamping Voltage @ IPP | VC | 9.8 | V | @ IPP = 1 A (Note 3) | 2 | ||
| Peak Power Dissipation | Ppk | 69 | W | (Note 3) | 2 | ||
| Maximum Reverse Leakage Current @ VRWM | IR1 | 0.5 | A | @ VRWM | 2 | ||
| Maximum Reverse Leakage Current @ VR | IR2 | 0.3 | A | @ VR = 3.5 V | 2 | ||
| Breakdown Voltage @ IT | VBR | 5.6 | V | @ IT = 1.0 mA (Note 2), TA = 25°C | 2 | ||
| Capacitance | C | 15 | pF | @ VR = 0 and f = 1.0 MHz | 2 | ||
| Working Peak Reverse Voltage | VRWM | 5 | V | 2 | |||
| Total Power Dissipation on FR-5 Board | PD | 200 | mW | @ TA = 25°C (Note 1, FR-5 = 1.00.750.62 in.) | 1 | ||
| Junction and Storage Temperature Range | TJ,TSTG | -55 | 150 | °C | 1 | ||
| Lead Solder Temperature, Maximum (10 second duration) | TL | 260 | °C | 10 second duration | 1 | ||
| ESD Voltage Per Human Body Model | 16 | kV | Human Body Model | 1 | |||
| IEC 61000-4-2 (ESD) Air discharge | -25 | 25 | kV | IEC 61000-4-2, air discharge | 1 | ||
| IEC 61000-4-2 (ESD) Contact discharge | -20 | 20 | kV | IEC 61000-4-2, contact discharge | 1 |
CAD (KiCad official)
- Symbol:
LESD8D5.0CN3T6G - Footprint:
Package_TO_SOT_SMD:SOT-883 - 3D model: SOT-883, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.45 mm nominal SOT height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lesd8d5-0cn3t6g-etched.step/lesd8d5-0cn3t6g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lesd8d5-0cn3t6g.step/lesd8d5-0cn3t6g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (4 pp, sha256
db0d059acca34f6b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).