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STM32L471ZGT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32L471ZGT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

STM32L471ZGT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant (FT) I/O, analog input at reset; alternate functions TRACECK, TIM3_ETR, TSC_G7_IO1, FMC_A23, SAI1_MCLK_A, EVENTOUT.
2 PE3 bidirectional 5 V-tolerant (FT) I/O, analog input at reset; alternate functions TRACED0, TIM3_CH1, TSC_G7_IO2, FMC_A19, SAI1_SD_B, EVENTOUT.
3 PE4 bidirectional 5 V-tolerant (FT) I/O, analog input at reset; alternate functions TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, FMC_A20, SAI1_FS_A, EVENTOUT.
4 PE5 bidirectional 5 V-tolerant (FT) I/O, analog input at reset; alternate functions TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, FMC_A21, SAI1_SCK_A, EVENTOUT.
5 PE6 bidirectional 5 V-tolerant (FT) I/O, analog input at reset; alternate functions TRACED3, TIM3_CH4, FMC_A22, SAI1_SD_A, EVENTOUT; additional function RTC_TAMP3/WKUP3.
6 VBAT power_in Backup domain supply, 1.55 V to 3.6 V, powering the RTC and backup registers (Table 23).
7 PC13 bidirectional 5 V-tolerant (FT) I/O supplied through the power switch; sink limited to 3 mA, speed at most 2 MHz with 30 pF load, and must not be used as a current source (Table 16 note 1).
8 PC14-OSC32_IN bidirectional 5 V-tolerant (FT) I/O supplied through the power switch with the same limits as PC13 (3 mA sink, 2 MHz / 30 pF); also LSE oscillator input OSC32_IN (Table 16 notes 1-2).
9 PC15-OSC32_OUT bidirectional 5 V-tolerant (FT) I/O supplied through the power switch with the same limits as PC13 (3 mA sink, 2 MHz / 30 pF); also LSE oscillator output OSC32_OUT (Table 16 notes 1-2).
10 PF0 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions I2C2_SDA, FMC_A0, EVENTOUT.
11 PF1 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions I2C2_SCL, FMC_A1, EVENTOUT.
12 PF2 bidirectional 5 V-tolerant (FT) I/O; alternate functions I2C2_SMBA, FMC_A2, EVENTOUT.
13 PF3 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions FMC_A3, EVENTOUT; additional function ADC3_IN6.
14 PF4 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions FMC_A4, EVENTOUT; additional function ADC3_IN7.
15 PF5 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions FMC_A5, EVENTOUT; additional function ADC3_IN8.
16 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
17 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
18 PF6 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM5_ETR, TIM5_CH1, SAI1_SD_B, EVENTOUT; additional function ADC3_IN9.
19 PF7 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM5_CH2, SAI1_MCLK_B, EVENTOUT; additional function ADC3_IN10.
20 PF8 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM5_CH3, SAI1_SCK_B, EVENTOUT; additional function ADC3_IN11.
21 PF9 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM5_CH4, SAI1_FS_B, TIM15_CH1, EVENTOUT; additional function ADC3_IN12.
22 PF10 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM15_CH2, EVENTOUT; additional function ADC3_IN13.
23 PH0-OSC_IN bidirectional 5 V-tolerant (FT) I/O; also high-speed external oscillator input OSC_IN, alternate function EVENTOUT.
24 PH1-OSC_OUT bidirectional 5 V-tolerant (FT) I/O; also high-speed external oscillator output OSC_OUT, alternate function EVENTOUT.
25 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor (RST structure).
26 PC0 bidirectional 5 V-tolerant I/O with Fm+ capability and analog switch supplied by VDDA (FT_fa); alternate functions LPTIM1_IN1, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX, LPTIM2_IN1, EVENTOUT; additional function ADC123_IN1.
27 PC1 bidirectional 5 V-tolerant I/O with Fm+ capability and analog switch supplied by VDDA (FT_fa); alternate functions LPTIM1_OUT, I2C3_SDA, DFSDM1_CKIN4, LPUART1_TX, EVENTOUT; additional function ADC123_IN2.
28 PC2 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, EVENTOUT; additional function ADC123_IN3.
29 PC3 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR, EVENTOUT; additional function ADC123_IN4.
30 VSSA power_in Analog ground for the ADC, DAC, OPAMP, COMP and voltage reference.
31 VREF- power_in Negative ADC reference voltage, equal to VSSA (Table 66).
32 VREF+ power_in Positive ADC reference: at least 2 V when VDDA is 2 V or higher, otherwise equal to VDDA (Table 66); also VREFBUF_OUT.
33 VDDA power_in Analog supply: 1.62 V minimum for ADC or COMP, 1.8 V for DAC or OPAMP, 2.4 V for VREFBUF, up to 3.6 V (Table 23).
34 PA0 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI1_EXTCLK, TIM2_ETR, EVENTOUT; additional functions OPAMP1_VINP, ADC12_IN5, RTC_TAMP2/WKUP1.
35 PA1 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM2_CH2, TIM5_CH2, USART2_RTS_DE, UART4_RX, TIM15_CH1N, EVENTOUT; additional functions OPAMP1_VINM, ADC12_IN6.
36 PA2 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); alternate functions TIM2_CH3, TIM5_CH3, USART2_TX, SAI2_EXTCLK, TIM15_CH1, EVENTOUT; additional functions ADC12_IN7, WKUP4/LSCO.
37 PA3 bidirectional 3.6 V-tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM2_CH4, TIM5_CH4, USART2_RX, TIM15_CH2, EVENTOUT; additional functions OPAMP1_VOUT, ADC12_IN8.
38 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
39 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
40 PA4 bidirectional 3.6 V-tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT; additional functions ADC12_IN9, DAC1_OUT1.
41 PA5 bidirectional 3.6 V-tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR, EVENTOUT; additional functions ADC12_IN10, DAC1_OUT2.
42 PA6 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, USART3_CTS, QUADSPI_BK1_IO3, TIM16_CH1, EVENTOUT; additional functions OPAMP2_VINP, ADC12_IN11.
43 PA7 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, QUADSPI_BK1_IO2, TIM17_CH1, EVENTOUT; additional functions OPAMP2_VINM, ADC12_IN12.
44 PC4 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions USART3_TX, EVENTOUT; additional functions COMP1_INM, ADC12_IN13.
45 PC5 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate function USART3_RX, EVENTOUT; additional functions COMP1_INP, ADC12_IN14, WKUP5.
46 PB0 bidirectional 3.6 V-tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT, EVENTOUT; additional functions OPAMP2_VOUT, ADC12_IN15.
47 PB1 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1, EVENTOUT; additional functions COMP1_INM, ADC12_IN16.
48 PB2 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0, EVENTOUT; additional function COMP1_INP.
49 PF11 bidirectional 5 V-tolerant (FT) I/O; alternate function EVENTOUT.
50 PF12 bidirectional 5 V-tolerant (FT) I/O; alternate functions FMC_A6, EVENTOUT.
51 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
52 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
53 PF13 bidirectional 5 V-tolerant (FT) I/O; alternate functions DFSDM1_DATIN6, FMC_A7, EVENTOUT.
54 PF14 bidirectional 5 V-tolerant (FT) I/O; alternate functions DFSDM1_CKIN6, TSC_G8_IO1, FMC_A8, EVENTOUT.
55 PF15 bidirectional 5 V-tolerant (FT) I/O; alternate functions TSC_G8_IO2, FMC_A9, EVENTOUT.
56 PG0 bidirectional 5 V-tolerant (FT) I/O; alternate functions TSC_G8_IO3, FMC_A10, EVENTOUT.
57 PG1 bidirectional 5 V-tolerant (FT) I/O; alternate functions TSC_G8_IO4, FMC_A11, EVENTOUT.
58 PE7 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B, EVENTOUT.
59 PE8 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B, EVENTOUT.
60 PE9 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B, EVENTOUT.
61 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
62 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
63 PE10 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B, EVENTOUT.
64 PE11 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, QUADSPI_NCS, FMC_D8, EVENTOUT.
65 PE12 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9, EVENTOUT.
66 PE13 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10, EVENTOUT.
67 PE14 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11, EVENTOUT.
68 PE15 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12, EVENTOUT.
69 PB10 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions TIM2_CH3, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, QUADSPI_CLK, COMP1_OUT, SAI1_SCK_A, EVENTOUT.
70 PB11 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions TIM2_CH4, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_NCS, COMP2_OUT, EVENTOUT.
71 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
72 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
73 PB12 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN, EVENTOUT.
74 PB13 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N, EVENTOUT.
75 PB14 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1, EVENTOUT.
76 PB15 bidirectional 5 V-tolerant (FT) I/O; alternate functions RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2, EVENTOUT.
77 PD8 bidirectional 5 V-tolerant (FT) I/O; alternate functions USART3_TX, FMC_D13, EVENTOUT.
78 PD9 bidirectional 5 V-tolerant (FT) I/O; alternate functions USART3_RX, FMC_D14, SAI2_MCLK_A, EVENTOUT.
79 PD10 bidirectional 5 V-tolerant (FT) I/O; alternate functions USART3_CK, TSC_G6_IO1, FMC_D15, SAI2_SCK_A, EVENTOUT.
80 PD11 bidirectional 5 V-tolerant (FT) I/O; alternate functions USART3_CTS, TSC_G6_IO2, FMC_A16, SAI2_SD_A, LPTIM2_ETR, EVENTOUT.
81 PD12 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM4_CH1, USART3_RTS_DE, TSC_G6_IO3, FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT.
82 PD13 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM4_CH2, TSC_G6_IO4, FMC_A18, LPTIM2_OUT, EVENTOUT.
83 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
84 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
85 PD14 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM4_CH3, FMC_D0, EVENTOUT.
86 PD15 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM4_CH4, FMC_D1, EVENTOUT.
87 PG2 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions SPI1_SCK, FMC_A12, SAI2_SCK_B, EVENTOUT.
88 PG3 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions SPI1_MISO, FMC_A13, SAI2_FS_B, EVENTOUT.
89 PG4 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions SPI1_MOSI, FMC_A14, SAI2_MCLK_B, EVENTOUT.
90 PG5 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions SPI1_NSS, LPUART1_CTS, FMC_A15, SAI2_SD_B, EVENTOUT.
91 PG6 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions I2C3_SMBA, LPUART1_RTS_DE, EVENTOUT.
92 PG7 bidirectional 5 V-tolerant I/O with Fm+ capability, supplied only by VDDIO2 (FT_fs); alternate functions I2C3_SCL, LPUART1_TX, FMC_INT, EVENTOUT.
93 PG8 bidirectional 5 V-tolerant I/O with Fm+ capability, supplied only by VDDIO2 (FT_fs); alternate functions I2C3_SDA, LPUART1_RX, EVENTOUT.
94 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
95 VDDIO2 power_in Supply for the PG[15:2] I/Os, 1.08 V to 3.6 V when at least one PG[15:2] I/O is used, or 0 to 3.6 V if none are used (Table 23).
96 PC6 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, SDMMC1_D6, SAI2_MCLK_A, EVENTOUT.
97 PC7 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, SDMMC1_D7, SAI2_MCLK_B, EVENTOUT.
98 PC8 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_CH3, TIM8_CH3, TSC_G4_IO3, SDMMC1_D0, EVENTOUT.
99 PC9 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM8_BKIN2, TIM3_CH4, TIM8_CH4, TSC_G4_IO4, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1, EVENTOUT.
100 PA8 bidirectional 5 V-tolerant (FT) I/O; alternate functions MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT, EVENTOUT.
101 PA9 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH2, USART1_TX, TIM15_BKIN, EVENTOUT.
102 PA10 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH3, USART1_RX, TIM17_BKIN, EVENTOUT.
103 PA11 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1, EVENTOUT.
104 PA12 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_ETR, USART1_RTS_DE, CAN1_TX, EVENTOUT.
105 PA13 bidirectional 5 V-tolerant (FT) I/O; JTMS-SWDIO debug function after reset with internal pull-up active (Table 16 note 4); alternate functions IR_OUT, EVENTOUT.
106 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
107 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
108 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
109 PA14 bidirectional 5 V-tolerant (FT) I/O; JTCK-SWCLK debug function after reset with internal pull-down active (Table 16 note 4); alternate function EVENTOUT.
110 PA15 (JTDI) bidirectional 5 V-tolerant (FT) I/O; JTDI debug function after reset with internal pull-up active (Table 16 note 4); alternate functions TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, UART4_RTS_DE, TSC_G3_IO1, SAI2_FS_B, EVENTOUT.
111 PC10 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, SDMMC1_D2, SAI2_SCK_B, EVENTOUT.
112 PC11 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, SDMMC1_D3, SAI2_MCLK_B, EVENTOUT.
113 PC12 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, SDMMC1_CK, SAI2_SD_B, EVENTOUT.
114 PD0 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2, EVENTOUT.
115 PD1 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3, EVENTOUT.
116 PD2 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, SDMMC1_CMD, EVENTOUT.
117 PD3 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, FMC_CLK, EVENTOUT.
118 PD4 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, FMC_NOE, EVENTOUT.
119 PD5 bidirectional 5 V-tolerant (FT) I/O; alternate functions USART2_TX, FMC_NWE, EVENTOUT.
120 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
121 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).
122 PD6 bidirectional 5 V-tolerant (FT) I/O; alternate functions DFSDM1_DATIN1, USART2_RX, FMC_NWAIT, SAI1_SD_A, EVENTOUT.
123 PD7 bidirectional 5 V-tolerant (FT) I/O; alternate functions DFSDM1_CKIN1, USART2_CK, FMC_NE1, EVENTOUT.
124 PG9 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions SPI3_SCK, USART1_TX, FMC_NCE/FMC_NE2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT.
125 PG10 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions LPTIM1_IN1, SPI3_MISO, USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1, EVENTOUT.
126 PG11 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions LPTIM1_IN2, SPI3_MOSI, USART1_CTS, SAI2_MCLK_A, TIM15_CH2, EVENTOUT.
127 PG12 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions LPTIM1_ETR, SPI3_NSS, USART1_RTS_DE, FMC_NE4, SAI2_SD_A, EVENTOUT.
128 PG13 bidirectional 5 V-tolerant I/O with Fm+ capability, supplied only by VDDIO2 (FT_fs); alternate functions I2C1_SDA, USART1_CK, FMC_A24, EVENTOUT.
129 PG14 bidirectional 5 V-tolerant I/O with Fm+ capability, supplied only by VDDIO2 (FT_fs); alternate functions I2C1_SCL, FMC_A25, EVENTOUT.
130 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
131 VDDIO2 power_in Supply for the PG[15:2] I/Os, 1.08 V to 3.6 V when at least one PG[15:2] I/O is used (Table 23).
132 PG15 bidirectional 5 V-tolerant I/O supplied only by VDDIO2 (FT_s); alternate functions LPTIM1_OUT, I2C1_SMBA, EVENTOUT.
133 PB3 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); JTDO-TRACESWO debug function after reset (Table 16 note 4); alternate functions TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B, EVENTOUT; additional function COMP2_INM.
134 PB4 bidirectional I/O with analog switch supplied by VDDA (FT_a, 5 V-tolerant); NJTRST debug function after reset with internal pull-up active (Table 16 note 4); alternate functions TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, SAI1_MCLK_B, TIM17_BKIN, EVENTOUT; additional function COMP2_INP.
135 PB5 bidirectional 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT.
136 PB6 bidirectional 5 V-tolerant I/O with Fm+ capability and analog switch supplied by VDDA (FT_fa); alternate functions LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, DFSDM1_DATIN5, USART1_TX, TSC_G2_IO3, TIM8_BKIN2_COMP2, SAI1_FS_B, TIM16_CH1N, EVENTOUT; additional function COMP2_INP.
137 PB7 bidirectional 5 V-tolerant I/O with Fm+ capability and analog switch supplied by VDDA (FT_fa); alternate functions LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, FMC_NL, TIM8_BKIN_COMP1, TIM17_CH1N, EVENTOUT; additional functions COMP2_INM, PVD_IN.
138 BOOT0 input Dedicated BOOT0 pin selecting the boot mode; input voltage range 0 V to 9 V (Table 23).
139 PB8 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT.
140 PB9 bidirectional 5 V-tolerant I/O with Fm+ capability (FT_f); alternate functions IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, SDMMC1_D5, SAI1_FS_A, TIM17_CH1, EVENTOUT.
141 PE0 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM4_ETR, FMC_NBL0, TIM16_CH1, EVENTOUT.
142 PE1 bidirectional 5 V-tolerant (FT) I/O; alternate functions FMC_NBL1, TIM17_CH1, EVENTOUT.
143 VSS power_in Ground; all VSS pins must be connected to the ground plane (Table 20 note 1).
144 VDD power_in Standard supply, 1.71 V to 3.6 V (Table 23).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: STM32L471ZGT6
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: stm32l471zgt6-etched.step / stm32l471zgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l471zgt6.step / stm32l471zgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (229 pp, sha256 2a91fd04e0793619, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF