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XD74LS190

Public Made by Adom

by adom

XINLUDA Counters, Dividers, DIP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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XD74LS190

XINLUDA · Counters, Dividers · DIP-16

XD74LS190 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Data input B, preset data entered when Load is low.
2 QB output Counter output QB from the master-slave flip-flops; IOL max 8 mA, IOH max -400 uA.
3 QA output Counter output QA from the master-slave flip-flops; IOL max 8 mA, IOH max -400 uA.
4 G input Active-low Enable input; a low allows counting on the clock low-to-high transition and a high inhibits counting.
5 Down/Up input Direction control input; low counts up, high counts down, and changes should be made only when clock is high.
6 QC output Counter output QC from the master-slave flip-flops; IOL max 8 mA, IOH max -400 uA.
7 QD output Counter output QD from the master-slave flip-flops; IOL max 8 mA, IOH max -400 uA.
8 GND power_in Ground, the 0 V reference for the supply.
9 D input Data input D, preset data entered when Load is low.
10 C input Data input C, preset data entered when Load is low.
11 Load input Active-low asynchronous load input; a low presets the outputs to the data inputs independently of the clock.
12 Max/Min output Maximum/minimum count output; gives a high pulse about one clock cycle long on overflow or underflow, for look-ahead cascading.
13 Ripple Clock output Active-low ripple clock output; gives a low pulse equal to the low portion of the clock on overflow or underflow, for cascading.
14 Clock input Clock input, triggered on the low-to-high transition when Enable is low; maximum clock frequency 20 MHz.
15 A input Data input A, preset data entered when Load is low.
16 VCC power_in Positive supply, recommended 4.75 to 5.25 V (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V 4
Input voltage VIN 7 V 4
Power dissipation PT 400 mW 4
Storage temperature Tstg -65 150 C 4
Supply voltage VCC 4.75 5 5.25 V 4
Output current (high) IOH -400 A 4
Output current (low) IOL 8 mA 4
Operating temperature Topr -20 25 75 C 4
Clock frequency 0 20 MHz 4
Clock pulse width tw (CK) 25 ns 4
Load pulse width tw (Load) 35 ns 4
Setup time tsu 20 ns 4
Hold time (data) th (data) 3 ns 4
Enable time tenable 40 ns 4
Input voltage (high) VIH 2 V 4
Input voltage (low) VIL 0.8 V 4
Output voltage (high) VOH 2.7 V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 4
Output voltage (low) VOL 0.4 V IOL = 4 mA 4
Output voltage (low) VOL 0.5 V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOL = 8 mA 4
Input current high (Enable) IIH 60 A VCC = 5.25 V, VI = 2.7 V 4
Input current high (Others) IIH 20 A VCC = 5.25 V, VI = 2.7 V 4
Input current low (Enable) IIL -1.2 mA VCC = 5.25 V, VI = 0.4 V 4
Input current low (Others) IIL -0.4 mA VCC = 5.25 V, VI = 0.4 V 4
Input current at maximum input voltage (Enable) II 0.3 mA VCC = 5.25 V, VI = 7 V 4
Input current at maximum input voltage (Others) II 0.1 mA VCC = 5.25 V, VI = 7 V 4
Short-circuit output current IOS -20 -100 mA VCC = 5.25 V 4
Supply current ICC 20 35 mA VCC = 5.25 V 4
Input clamp voltage VIK -1.5 V VCC = 4.75 V, IIN = -18 mA 4
Maximum clock frequency max 20 25 MHz CL = 15 pF, RL = 2 k 5
Propagation delay time Load to QA-QD (low-to-high) tPLH 22 33 ns 5
Propagation delay time Load to QA-QD (high-to-low) tPHL 33 50 ns 5
Propagation delay time A, B, C, D to QA-QD (low-to-high) tPLH 20 32 ns 5
Propagation delay time A, B, C, D to QA-QD (high-to-low) tPHL 27 40 ns 5
Propagation delay time Clock to Ripple Clock (low-to-high) tPLH 13 20 ns 5
Propagation delay time Clock to Ripple Clock (high-to-low) tPHL 16 24 ns 5
Propagation delay time Clock to QA-QD (low-to-high) tPLH 16 24 ns 5
Propagation delay time Clock to QA-QD (high-to-low) tPHL 24 36 ns 5
Propagation delay time Clock to Max/Min (low-to-high) tPLH 28 42 ns 5
Propagation delay time Clock to Max/Min (high-to-low) tPHL 37 52 ns 5
Propagation delay time Down/Up to Ripple Clock (low-to-high) tPLH 30 45 ns 5
Propagation delay time Down/Up to Ripple Clock (high-to-low) tPHL 30 45 ns 5
Propagation delay time Down/Up to Max/Min (low-to-high) tPLH 21 33 ns 5
Propagation delay time Down/Up to Max/Min (high-to-low) tPHL 22 33 ns 5
Propagation delay time Enable to Ripple Clock (low-to-high) tPLH 21 33 ns 5
Propagation delay time Enable to Ripple Clock (high-to-low) tPHL 22 33 ns 5

CAD (KiCad official)

  • Symbol: XD74LS190
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd74ls190-etched.step / xd74ls190-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls190.step / xd74ls190.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (10 pp, sha256 53f5818b6d625de6, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF