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ESP32-H2FH4

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Espressif Systems Microcontrollers (MCU/MPU/SOC), QFN-32(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersesp32-h2fh4factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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ESP32-H2FH4

Espressif Systems · Microcontrollers (MCU/MPU/SOC) · QFN-32(4x4)

ESP32-H2FH4 from Espressif Systems, in a QFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD3P3 power_in Analog power domain supply input, recommended 3.0-3.6 V (3.3 V typical), with absolute maximum input voltage of -0.3 to 3.6 V.
2 VDD3P3 power_in Analog power domain supply input, recommended 3.0-3.6 V (3.3 V typical), with absolute maximum input voltage of -0.3 to 3.6 V.
3 GPIO0 bidirectional General-purpose I/O on the VDDPST1 digital IO domain, selectable via IO MUX (F0 GPIO0, F1 FSPIQ via SPI2); it cannot operate in Deep-sleep mode and can only operate in Light-sleep if the XPD_TOP power domain stays powered.
4 GPIO1 bidirectional General-purpose I/O on the VDDPST1 digital IO domain, also serving as ADC1 channel 0 analog input and FSPICS0 SPI2 chip select via IO MUX; it cannot operate in Deep-sleep mode.
5 MTMS bidirectional JTAG test mode select on the VDDPST1 IO domain (alternate function GPIO2, ADC1 channel 1), with input enabled at reset.
6 MTDO bidirectional JTAG test data output on the VDDPST1 IO domain (alternate function GPIO3, ADC1 channel 2), with input enabled at reset.
7 MTCK bidirectional JTAG test clock input on the VDDPST1 IO domain (alternate function GPIO4, ADC1 channel 3); its input enable is marked with a footnote in the pin table, see chapter 2.
8 MTDI bidirectional JTAG test data input on the VDDPST1 IO domain (alternate function GPIO5, ADC1 channel 4), with input enabled at reset.
9 VDDPST1 power_in IO power domain supply for digital IO and LP IO pins, recommended 3.0-3.6 V (3.3 V typical).
10 GPIO8 bidirectional Strapping pin sampled at reset that, together with GPIO9, selects the boot mode and also controls UART0 ROM log printing; it is floating by default and is an LP IO.
11 GPIO9 bidirectional Strapping pin sampled at reset that, together with GPIO8, selects the boot mode (weak pull-up by default, so it reads 1 unless driven low externally).
12 GPIO10 bidirectional General-purpose I/O on the VDDPST1 IO domain, also serving as analog pad voltage comparator input ZCD0.
13 GPIO11 bidirectional General-purpose I/O on the VDDPST1 IO domain, also serving as analog pad voltage comparator input ZCD1.
14 GPIO12 bidirectional LP general-purpose I/O powered from the VDDA_PMU/VBAT domain, usable in any chip power mode.
15 XTAL_32K_P bidirectional Positive terminal of the external 32 kHz crystal (or external slow clock input, default 32 kHz), powered from the VDDA_PMU/VBAT domain.
16 XTAL_32K_N bidirectional Negative terminal of the external 32 kHz crystal, powered from the VDDA_PMU/VBAT domain.
17 CHIP_EN input Chip enable: high powers up the chip and low powers it down/resets it, with a VIH of 0.75×VDD to VDD+0.3 V and must not be left floating.
18 VBAT power_in Supply input for the analog power domain or battery power, feeding GPIO12, XTAL_32K_P and XTAL_32K_N.
19 VDDA_PMU power_in Analog power domain supply input for the power management unit, feeding GPIO12, XTAL_32K_P and XTAL_32K_N.
20 VDDPST2 power_in IO power domain supply for digital IO pins GPIO22 through GPIO27, recommended 3.0-3.6 V; when writing eFuse it must not exceed 3.3 V.
21 GPIO22 bidirectional General-purpose digital I/O on the VDDPST2 IO domain; it cannot operate in Deep-sleep mode.
22 U0RXD bidirectional UART0 receive signal on the VDDPST2 IO domain (alternate function GPIO23), with input enabled and weak pull-up at reset.
23 U0TXD bidirectional UART0 transmit signal on the VDDPST2 IO domain (alternate function GPIO24), with input enabled and weak pull-up at reset.
24 GPIO25 bidirectional Strapping pin sampled at reset that controls the JTAG signal source; it has no internal pull-up or pull-down and must be driven by an external circuit that is not high-impedance.
25 GPIO26 bidirectional General-purpose I/O on the VDDPST2 IO domain that doubles as USB_D- for the USB Serial/JTAG controller; its default drive current is 40 mA.
26 GPIO27 bidirectional General-purpose I/O on the VDDPST2 IO domain that doubles as USB_D+ for the USB Serial/JTAG controller, with USB pull-up enabled by default; its default drive current is 40 mA.
27 VDD3P3 power_in Analog power domain supply input, recommended 3.0-3.6 V (3.3 V typical), with absolute maximum input voltage of -0.3 to 3.6 V.
28 XTAL_N passive Negative terminal of the external 32 MHz crystal (active or passive); the chip cannot operate without an external crystal clock.
29 XTAL_P passive Positive terminal of the external 32 MHz crystal (active or passive); the chip cannot operate without an external crystal clock.
30 VDD3P3 power_in Analog power domain supply input, recommended 3.0-3.6 V (3.3 V typical), with absolute maximum input voltage of -0.3 to 3.6 V.
31 VDD3P3 power_in Analog power domain supply input, recommended 3.0-3.6 V (3.3 V typical), with absolute maximum input voltage of -0.3 to 3.6 V.
32 ANT bidirectional RF input and output pin for the 2.4 GHz antenna.
33 GND power_in External ground reference pin.

Key specifications

Parameter Value
Manufacturer Espressif Systems
Package QFN-32(4x4)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: ESP32-H2FH4
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32(4x4) (KiCad packages3D, STEP)
  • 3D model files: esp32-h2fh4-etched.step / esp32-h2fh4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esp32-h2fh4.step / esp32-h2fh4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Espressif Systems datasheet (63 pp, sha256 86a469824007b789, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF