ISPPAC-POWR607-01SN24I from Lattice, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VMON1	input	Analog voltage monitor input rated -0.3 V to 5.9 V that can be biased independently from VCC; tie to GND if unused.
2	VMON2	input	Analog voltage monitor input rated -0.3 V to 5.9 V that can be biased independently from VCC; tie to GND if unused.
3	VCC	power_in	Core supply pin, 2.64 V to 3.96 V; both VCC pins (3 and 16) must be connected together on the board.
4	VMON3	input	Analog voltage monitor input rated -0.3 V to 5.9 V that can be biased independently from VCC; tie to GND if unused.
5	VMON4	input	Analog voltage monitor input rated -0.3 V to 5.9 V that can be biased independently from VCC; tie to GND if unused.
6	VMON5	input	Analog voltage monitor input rated -0.3 V to 5.9 V that can be biased independently from VCC; tie to GND if unused.
7	VMON6	input	Analog voltage monitor input rated -0.3 V to 5.9 V that can be biased independently from VCC; tie to GND if unused.
8	GND	power_in	Ground; all GND pins must be connected together on the circuit board.
9	GND	power_in	Ground; all GND pins must be connected together on the circuit board.
10	VCCJ	power_in	JTAG logic interface supply, 2.25 V to 3.6 V; it is pulled to GND in power-down mode, so it must be left open whenever power-down is initiated.
11	TDO	output	JTAG test data output, 0 V to 5.5 V.
12	TCK	input	JTAG test clock input, 0 V to 5.5 V.
13	TDI	input	JTAG test data input, 0 V to 5.5 V, with an internal pull-up.
14	TMS	input	JTAG test mode select input, 0 V to 5.5 V, with an internal pull-up.
15	IN_OUT7	bidirectional	Digital input 0 V to 5.5 V (PLD input 7, thresholds referenced to VCC) or open-drain output 7 that requires an external pull-up to a supply.
16	VCC	power_in	Core supply pin, 2.64 V to 3.96 V; both VCC pins (3 and 16) must be connected together on the board.
17	IN_OUT6	bidirectional	Digital input 0 V to 5.5 V (PLD input 6, thresholds referenced to VCC) or open-drain output 6 that requires an external pull-up to a supply.
18	IN_OUT5	bidirectional	Digital input 0 V to 5.5 V (PLD input 5, thresholds referenced to VCC) or open-drain output 5 that requires an external pull-up to a supply.
19	IN_OUT4	bidirectional	Digital input 0 V to 5.5 V (PLD input 4, thresholds referenced to VCC) or open-drain output 4 that requires an external pull-up to a supply.
20	IN_OUT3	bidirectional	Digital input 0 V to 5.5 V (PLD input 3, thresholds referenced to VCC) or open-drain output 3 that requires an external pull-up to a supply.
21	IN2	input	PLD logic input 2 rated 0 V to 5.5 V with thresholds referenced to VCC; tie to GND when not used.
22	IN1_PWRDN	input	PLD logic input 1 rated 0 V to 5.5 V that can serve as the power-down input (low enters, high exits power-down); pull down with a 10 k resistor when not used.
23	HVOUT1	output	Open-drain output rated 0 V to 10 V, or high-voltage FET gate driver rated 0 V to 9 V; open-drain mode requires an external pull-up to a supply.
24	HVOUT2	output	Open-drain output rated 0 V to 10 V, or high-voltage FET gate driver rated 0 V to 9 V; open-drain mode requires an external pull-up to a supply.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Lattice
Package	QFN-24-EP(4x4)
Category	Power Management ICs
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Core supply	VCC	-0.5		4.5	V		4
JTAG logic supply	VCCJ	-0.5		6	V		4
Digital input voltage (all digital I/O pins)	VIN	-0.5		6	V		4
VMON input voltage	VMON	-0.5		6	V		4
Voltage applied to tri-stated pins HVOUT[1:2]	VTRI	-0.5		11	V	HVOUT[1:2]	4
Voltage applied to tri-stated pins IN_OUT[3:7]	VTRI	-0.5		6	V	IN_OUT[3:7]	4
Storage temperature	TS	-65		150	°C		4
Ambient temperature (absolute maximum)	TA	-65		125	°C		4
Maximum sink current on any output	ISINKMAX			23	mA		4
Core supply voltage at pin	VCC	2.64		3.96	V		4
JTAG logic supply voltage at pin	VCCJ	2.25		3.6	V		4
Input voltage at digital input pins	VIN	-0.3		5.5	V		4
Input voltage at VMON pins	VMON	-0.3		5.9	V		4
Open-drain output voltage	VOUT	-0.3		5.5	V	IN_OUT[3:7] pins	4
Open-drain output voltage	VOUT	-0.3		10.4	V	HVOUT[1:2] pins in open-drain mode	4
Ambient temperature during programming	TAPROG	-40		85	°C		4
Ambient temperature, power applied	TA	-40		105	°C	Power applied	4
Operating junction temperature, power applied	TJOP	-40		108	°C	Power applied	4
Supply current	ICC1		3.5	5	mA		4
Supply current	ICCJ2			1	mA		4
Power-down mode supply current	ICC_PWRDN			10	µA	ICC + pin leakage currents	4
Input resistance	RIN	55	65	75	k		5
Input capacitance	CIN		8		pF		5
Programmable trip-point range	VMON	0.075		5.811	V		5
Near-ground sense threshold	VZ	70	75	80	mV		5
Absolute accuracy of any trip-point	VMON Accuracy	-0.5		1.5	%		5
Hysteresis of any trip-point (relative to setting)	HYST		1		%		5
Gate driver output voltage	VPP	8.1	9	9.9	V		5
Gate driver source current (HIGH state)	IOUTSRC		15		µA	Controlled ramp setting	5
Gate driver sink current (LOW state)	IOUTSINK	1		2.5	mA	FET turn off mode	5
Delay from VTH to start-up state	TRST		100		µs		5
Duration of start-up state	TSTART		300		µs		5
Minimum duration brown out required to enter reset state	TBRO	1		5	µs		5
Delay from brown out to reset state	TPOR		7		µs		5
Threshold below which POR is LOW	VTL		2.2		V		5
Threshold above which POR is HIGH	VTH		2.5		V		5
Threshold above which POR is valid	VT		0.8		V		5
Propagation delay input to output, glitch filter OFF	tPD12		12		µs		7
Propagation delay input to output, glitch filter ON	tPD48		48		µs		7
PLDCLK frequency	fPLDCLK	240	250	260	kHz		7
Range of programmable timers (128 steps)	Timeout Range	0.032		1966	ms		7
Spacing between available adjacent timer intervals	Resolution		13		%		7
Timer accuracy	Accuracy	-12.5		-6.67	%		7
Time to enter power-down mode	TPWRDN		100		µs	Device previously on	7
Minimum required time in power-down mode before power-up can occur	TPWRDN_HOLD		100		µs		7
Time to exit power-down mode	TPWRUP		300		µs		7
Total time to enter and then exit power-down mode	TPWRDN_UP		500		µs		7
Input leakage, no pull-up/pull-down	IIL,IIH	-10		10	µA		8
Output leakage current	IOH-HVOUT	35		60	µA	HVOUT[1:2] in open drain mode and pulled up to 10 V	8
Input pull-up current (TMS, TDI)	IPU		70		µA		8
Voltage input, logic low	VIL			0.8	V	TDI, TMS, TCK, IN[1:2], IN_OUT[3:7]; VCCJ = 3.3 V supply	8
Voltage input, logic low	VIL			0.7	V	TDI, TMS, TCK; VCCJ = 2.5 V supply	8
Voltage input, logic high	VIH	2			V	TDI, TMS, TCK, IN[1:2], IN_OUT[3:7]; VCCJ = 3.3 V supply	8
Voltage input, logic high	VIH	1.7			V	TDI, TMS, TCK; VCCJ = 2.5 V supply	8
Output low voltage	VOL			0.8	V	HVOUT[1:2] (open drain mode), ISINK = 10 mA	8
Output low voltage	VOL			0.4	V	TDO, ISINK = 4 mA	8
Sum of maximum current sink from all digital outputs	ISINKTOTAL			67	mA	All digital outputs	8
TCK maximum clock frequency	fMAX			25	MHz		9
Falling edge of TCK to valid output	tCO			10	ns		9

CAD (KiCad official)

Symbol: ISPPAC-POWR607-01SN24I
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: isppac-powr607-01sn24i-etched.step / isppac-powr607-01sn24i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isppac-powr607-01sn24i.step / isppac-powr607-01sn24i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Lattice datasheet (29 pp, sha256 f166d58af267941a, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ISPPAC-POWR607-01SN24I

Verified ISPPAC-POWR607-01SN24I

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README