N76E003AT20-T
Public Unreviewedby Ray
Nuvoton Tech Microcontrollers (MCU/MPU/SOC), TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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markdownN76E003AT20-T
Nuvoton Tech · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
N76E003AT20-T from Nuvoton Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.5/PWM2/IC6/T0/AIN4 | bidirectional | Port 0 bit 5. Multiplexed with PWM output channel 2 (PWM2), input capture channel 6 (IC6), Timer 0 external count/toggle output (T0), and ADC input channel 4 (AIN4). |
| 2 | P0.6/TXD/AIN3 | bidirectional | Port 0 bit 6. Multiplexed with UART0 transmit data output (TXD) and ADC input channel 3 (AIN3). TXD/RXD of UART0 are software swappable via UART0PX (AUXR1.2). |
| 3 | P0.7/RXD/AIN2 | bidirectional | Port 0 bit 7. Multiplexed with UART0 receive data input (RXD) and ADC input channel 2 (AIN2). |
| 4 | P2.0/RST | input | P2.0 is a general-purpose port 2 bit 0 input when RPD (CONFIG0.2) is programmed as 0. Otherwise operates as active-low external reset (RST), a Schmitt-trigger input with internal pull-up that resets the device when driven low. |
| 5 | P3.0/INT0/OSCIN/AIN1 | bidirectional | Port 3 bit 0 available when the internal oscillator is used as the system clock. Multiplexed with external interrupt 0 (INT0), external clock input (XIN/OSCIN) when ECLK mode enabled, and ADC input channel 1 (AIN1). |
| 6 | P1.7/INT1/AIN0 | bidirectional | Port 1 bit 7. Multiplexed with external interrupt 1 (INT1) and ADC input channel 0 (AIN0). |
| 7 | GND | power_in | Ground reference (0 V) for all supply and I/O domains. |
| 8 | P1.6/ICPDA/OCDDA/TXD_1/[SDA] | bidirectional | Port 1 bit 6. Multiplexed with In-Circuit Programming data (ICPDA), On-Chip Debugger data (OCDDA), UART1 transmit output (TXD_1), and optional I2C data (SDA) when I2C alternate-pin remapping is selected. |
| 9 | VDD | power_in | Positive supply voltage. Operating range 2.4 V to 5.5 V for core and I/O. |
| 10 | P1.5/PWM5/IC7/SS | bidirectional | Port 1 bit 5. Multiplexed with PWM output channel 5 (PWM5), input capture channel 7 (IC7), and SPI slave-select input (SS, active low). |
| 11 | P1.4/SDA/FB/PWM1 | bidirectional | Port 1 bit 4. Multiplexed with default I2C data (SDA), PWM Fault-Brake input (FB), and PWM output channel 1 (PWM1). |
| 12 | P1.3/SCL/[STADC] | bidirectional | Port 1 bit 3. Multiplexed with default I2C clock (SCL) and optional external ADC start trigger input (STADC) when STADC remap is selected. |
| 13 | P1.2/PWM0/IC0 | bidirectional | Port 1 bit 2. Multiplexed with PWM output channel 0 (PWM0) and input capture channel 0 (IC0). |
| 14 | P1.1/PWM1/IC1/AIN7/CLO | bidirectional | Port 1 bit 1. Multiplexed with PWM output channel 1 (PWM1), input capture channel 1 (IC1), ADC input channel 7 (AIN7), and system clock output (CLO). |
| 15 | P1.0/PWM2/IC2/SPCLK | bidirectional | Port 1 bit 0. Multiplexed with PWM output channel 2 (PWM2), input capture channel 2 (IC2), and SPI clock (SPCLK). |
| 16 | P0.0/PWM3/IC3/MOSI/T1 | bidirectional | Port 0 bit 0. Multiplexed with PWM output channel 3 (PWM3), input capture channel 3 (IC3), SPI MOSI (master output/slave input), and Timer 1 external count/toggle output (T1). |
| 17 | P0.1/PWM4/IC4/MISO | bidirectional | Port 0 bit 1. Multiplexed with PWM output channel 4 (PWM4), input capture channel 4 (IC4), and SPI MISO (master input/slave output). |
| 18 | P0.2/ICPCK/OCDCK/RXD_1/[SCL] | bidirectional | Port 0 bit 2. Multiplexed with In-Circuit Programming clock (ICPCK), On-Chip Debugger clock (OCDCK), UART1 receive input (RXD_1), and optional I2C clock (SCL) when I2C remap is selected. |
| 19 | P0.3/PWM5/IC5/AIN6 | bidirectional | Port 0 bit 3. Multiplexed with PWM output channel 5 (PWM5), input capture channel 5 (IC5), and ADC input channel 6 (AIN6). |
| 20 | P0.4/AIN5/STADC/PWM3/IC3 | bidirectional | Port 0 bit 4. Multiplexed with ADC input channel 5 (AIN5), default external ADC start trigger (STADC), PWM output channel 3 (PWM3), and input capture channel 3 (IC3). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nuvoton Tech |
| Package | TSSOP-20 |
| Category | MCU |
| Pins | 20 |
Ordering variants
Same part, different packaging or reel option.
N76E003AT20-TN76E003AT20-TAS20N76E003AT20-TAQ20N76E003AT20-TBQ20N76E003AT20-TCQ20
CAD (KiCad official)
- Symbol:
N76E003AT20-T - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
n76e003at20-t.step |
267 KB | You want the bare part, or you mark your own boards. |
n76e003at20-t-etched.step |
3.0 MB | You want the part with N76E003AT20-T already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 754 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nuvoton Tech datasheet (276 pp, sha256
3f20216500ad7679, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).