component
LW5215A23E
Public Made by Adomby adom
Lewa Micro Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLW5215A23E
Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5L
LW5215A23E from Lewa Micro, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input pin; use the recommended value or a larger ceramic capacitor from IN to ground, placed as close to the device as possible, with VIN specified at 1.5 V to 6.0 V. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable pin; drive above VEN(HI) (1.5 V typ/min per the electrical table) to turn the regulator on and below VEN(LO) (0.5 V) to put the LDO into shutdown, with EN pin voltage rated 0 V to 6.0 V. |
| 4 | NC | unconnected | No internal connection; the datasheet says to ground this pin for better thermal performance. |
| 5 | VOUT | power_out | Regulated output pin, with output voltage 1.2 V to 5.0 V and an internal pulldown that discharges OUT in shutdown; use a low-ESR capacitor of at least 1 µF from OUT to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Accuracy | VOUT | -1.5 | 1.5 | % | IOUT= 1mA | 5 | |
| Current Limit | ILIM | 515 | 700 | mA | 5 | ||
| Quiescent Current | IQ | 40 | 60 | μA | VIN= VEN=VOUT+1V, No Load | 5 | |
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | 0.1 | 0.25 | %/V | VIN= VOUT +1V to 6V, IOUT=1mA | 5 | |
| Load Regulation | ΔVOUT | 20 | 50 | mV | 1mA≤IOUT≤500mA | 5 | |
| Input Voltage | VIN | 1.5 | 6 | V | 4 | ||
| EN Pin Voltage | VEN | 0 | 6 | V | 4 | ||
| VOUT Pin Voltage | VOUT | 1.2 | 5 | V | Series range as printed; this part is 1.5V output | 4 | |
| Output Current | IOUT | 0 | 500 | mA | 4 | ||
| Junction Temperature Range | TJ | -40 | 125 | ℃ | 4 | ||
| VIN Supply Voltage | VIN | -0.3 | 7 | V | 4 | ||
| EN Pin Voltage | VEN | -0.3 | 7 | V | 4 | ||
| VOUT Pin Voltage | VOUT | -0.3 | V | Upper limit printed as (VIN+0.3) V | 4 | ||
| ESD Susceptibility, HBM | V(ESD) | -4000 | 4000 | V | Per ANSI/ESDA/JEDEC JS-001; printed as ±4000 | 4 | |
| Junction Temperature Range | TJ | -40 | 150 | ℃ | 4 | ||
| Storage Temperature Range | TSTG | -40 | 150 | ℃ | 4 | ||
| Lead Temperature (Soldering) | TSOLDER | 260 | ℃ | 10 s | 4 | ||
| Junction-to-ambient Thermal Resistance, SOT23-5L | RθJA | 285 | ℃/W | Device mounted on FR-4 PCB, per JESD51-3 | 4 |
CAD (KiCad official)
- Symbol:
LW5215A23E - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files:
lw5215a23e-etched.step/lw5215a23e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lw5215a23e.step/lw5215a23e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Lewa Micro datasheet (22 pp, sha256
554585e66fced619, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).