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LE25U20AFD-AH

Public Made by Adom

by adom

onsemi NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

LE25U20AFD-AH

onsemi · NOR FLASH · SOIC-8

LE25U20AFD-AH from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select: the device is active when this pin is low and deselected into standby when it is high.
2 SO output Serial data output: stored data is output synchronized to the falling edge of SCK, and the pin is high-impedance when the device is deselected.
3 WP input Write protect: the status register write protect (SRWP) takes effect when this pin is low.
4 VSS power_in Ground, supplies the 0 V supply voltage.
5 SI input Serial data input: data and addresses are input here and latched on the rising edge of SCK.
6 SCK input Serial clock: controls data input/output timing, with input latched on the rising edge and output on the falling edge.
7 HOLD input Hold: serial communication is suspended when this pin is low.
8 VDD power_in Power supply pin, supplies the 2.30 to 3.60 V supply voltage.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating supply voltage VDD 2.3 3.6 V 16
Operating ambient temperature Topr -40 85 °C 16
Maximum supply voltage VDD max -0.5 4.6 V With respect to VSS 16
DC voltage (all pins) VIN/VOUT -0.5 V With respect to VSS; upper limit VDD+0.5 16
Storage temperature Tstg -55 150 °C 16
Read mode operating current ICCR 6 mA CS = 0.1VDD, HOLD = WP = 0.9VDD, SI = 0.1VDD / 0.9VDD, SO = open, 30 MHz, VDD = VDD max 16
Write mode operating current (erase+page program) ICCW 15 mA VDD = VDD max, tSSE = 40 ms, tSE = 80 ms, tCHE = 160 ms, tPP = 5.0 ms 16
CMOS standby current ISB 50 µA CS = HOLD = WP = VDD, SI = VSS / VDD, SO = open, VDD = VDD max 16
Power-down standby current IDSB 10 µA CS = HOLD = WP = VDD, SI = VSS / VDD, SO = open, VDD = VDD max 16
Input leakage current ILI 2 µA VIN = VSS to VDD, VDD = VDD max 16
Output leakage current ILO 2 µA VIN = VSS to VDD, VDD = VDD max 16
Input low voltage VIL -0.3 V VDD = VDD max; upper limit 0.3VDD 16
Output low voltage VOL 0.2 V IOL = 100 µA, VDD = VDD min 16
Output low voltage VOL 0.4 V IOL = 1.6 mA, VDD = VDD min 16
Time from power-on to read operation tPU_READ 100 µs 16
Time from power-on to write operation tPU_WRITE 10 ms 16
Power-down time tPD 10 ms 16
Power-down voltage vBOT 0.2 V 16
Output pin capacitance CDQ 12 pF VDQ = 0 V, Ta = 25C, f = 1 MHz 16
Input pin capacitance CIN 6 pF VIN = 0 V, Ta = 25C, f = 1 MHz 16
Clock frequency fCLK 30 MHz 17
SCK logic high level pulse width tCLHI 16 ns 17
SCK logic low level pulse width tCLLO 16 ns 17
Input signal rising/falling time tRF 20 ns 17
CS setup time tCSS 10 ns 17
CS hold time tCSH 10 ns 17
Data setup time tDS 5 ns 17
Data hold time tDH 5 ns 17
CS wait pulse width tCPH 25 ns 17
Output high impedance time from CS tCHZ 15 ns 17
Output data time from SCK tV 15 ns 17
Output data hold time tHO 1 ns 17
HOLD setup time tHS 7 ns 17
HOLD hold time tHH 3 ns 17
Output low impedance time from HOLD tHLZ 9 ns 17
Output high impedance time from HOLD tHHZ 9 ns 17
WP setup time tWPS 20 ns 17
WP hold time tWPH 20 ns 17
Write status register time tSRW 5 15 ms 17
Page programming cycle time tPP 4 5 ms 17
Small sector erase cycle time tSSE 0.04 0.15 s 17
Sector erase cycle time tSE 0.08 0.25 s 17
Chip erase cycle time tCHE 0.25 1.6 s 17
Power-down time tDP 3 µs 17
Power-down recovery time tPRB 3 µs 17
Output low impedance time from SCK tCLZ 0 ns 17

CAD (KiCad official)

  • Symbol: LE25U20AFD-AH
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: le25u20afd-ah-etched.step / le25u20afd-ah-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); le25u20afd-ah.step / le25u20afd-ah.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (21 pp, sha256 c044296517a12bca, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF