component
CY8CMBR3110-SX2IT
Public Made by Adomby adom
Cypress Semicon Touch Sensors, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCY8CMBR3110-SX2IT
Cypress Semicon · Touch Sensors · SOIC-16
CY8CMBR3110-SX2IT from Cypress Semicon, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I2C SDA | bidirectional | I2C data line; pull up if unused. |
| 2 | I2C SCL | bidirectional | I2C clock line; pull up if unused. |
| 3 | CS0/PS0 | input | CapSense button / proximity sensor controlling GPO0; connect to ground if unused. |
| 4 | CS1/PS1 | input | CapSense button / proximity sensor controlling GPO1; connect to ground if unused. |
| 5 | CMOD | passive | External modulator capacitor pin; connect a 2.2 nF/5 V/X7R or NPO capacitor. |
| 6 | VCC | power_in | Internal regulator output; connect a 0.1-µF decoupling capacitor if VDD > 1.8 V, or short to VDD if VDD is 1.71 V to 1.89 V. |
| 7 | VDD | power_in | Power supply input (1.71 V to 5.5 V operation). |
| 8 | VSS | power_in | Ground. |
| 9 | CS5/GPO0 | bidirectional | CapSense button / general purpose output GPO0; if unused ground it (open-drain low) or leave open (strong drive). |
| 10 | CS6/GPO1 | bidirectional | CapSense button / general purpose output GPO1; if unused ground it (open-drain low) or leave open (strong drive). |
| 11 | CS7/GPO2 | bidirectional | CapSense button / general purpose output GPO2; if unused ground it (open-drain low) or leave open (strong drive). |
| 12 | CS8/GPO3 | bidirectional | CapSense button / general purpose output GPO3; if unused ground it (open-drain low) or leave open (strong drive). |
| 13 | CS2/GUARD | input | CapSense button controlling GPO2 / guard sensor; connect to ground if unused. |
| 14 | CS9/GPO4/HI/BUZ | bidirectional | CapSense button / GPO4 / host interrupt / buzzer output (SPO1); acts as AXRES reset during boot-up so must not be grounded at power-up, and leave open and disable via register if unused. |
| 15 | CS3 | input | CapSense button controlling GPO3; connect to ground if unused. |
| 16 | CS4/SH | bidirectional | CapSense button controlling GPO4 / shield electrode (SPO0); connect to ground if unused as CS, leave open if SH. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | SOIC-16 |
| Category | Sensors |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Max voltage on VDD pin relative to VSS | VDD_MAX | -0.5 | 6 | V | -40 °C to +85 °C TA, absolute maximum | 24 | |
| Max voltage on VDDIO pin relative to VSS | VDDIO_MAX | 0.5 | 6 | V | -40 °C to +85 °C TA, absolute maximum | 24 | |
| Max voltage on VCC pin relative to VSS | VCC_MAX | -0.5 | 1.89 | V | Absolute maximum | 24 | |
| ESD human body model | ESD_HBM | 2200 | V | Human body model ESD. | 24 | ||
| ESD charged device model | ESD_CDM | 500 | V | Charged device model ESD | 24 | ||
| Latch-up current limits | ILU | -140 | 140 | mA | Maximum/minimum current to any input or output, pin-to-pin or pin-to-supply | 24 | |
| Current per GPIO | IIO | 25 | mA | 24 | |||
| Operation temperature | TO | -40 | 25 | 85 | °C | Ambient temperature inside system enclosure | 24 |
| Junction temperature | TJ | -40 | 100 | °C | 24 | ||
| Chip supply voltage (VCC shorted to VDD) | VDD | 1.71 | 1.8 | 1.89 | V | VCC shorted to VDD | 24 |
| Chip supply voltage (VCC not shorted to VDD) | VDD | 1.8 | 5.5 | V | VCC not shorted to VDD. VCC connected to 0.1 µF decoupling capacitor | 24 | |
| Supply voltage I/O | VDDIO | 1.71 | V | 1.71 V < VDD < 1.89 V (max printed as VDD) | 24 | ||
| Maximum allowed ripple on power supply, DC to 10 MHz | VDD_RIPPLE | -50 | 50 | mV | +25 °C TA, VDD > 2 V, sensitivity ≥ 0.1 pF | 24 | |
| Maximum allowed ripple on power supply, DC to 10 MHz | VDD_RIPPLE | -25 | 25 | mV | +25 °C TA, VDD > 1.75 V, CP < 20 pF, sensitivity = 0.4 pF | 24 | |
| External regulator voltage bypass | CEFC | 0.1 | µF | Capacitor to be connected to the VCC pin; X5R ceramic ±10% or better | 24 | ||
| Power supply decoupling capacitor on VDD | CEXC | 1 | µF | X5R ceramic or better | 24 | ||
| Input capacitance on XRES pin | CIN_XRES | 7 | pF | 25 | |||
| Input voltage hysteresis on XRES pin | VHYSXRES | 200 | mV | VDD > 4.5 V | 25 | ||
| Pull-up resistor | RPULLUP | 3.5 | 5.6 | 8.5 | kΩ | 25 | |
| Output voltage LOW level | VOL | 0.6 | V | IOL = 4 mA at 1.8 V VDD | 25 | ||
| Pin capacitance | CPIN | 3 | 7 | pF | All VDD, all packages, all I/Os | 25 | |
| Maximum total sink chip current | ITOT_GPIO | 85 | mA | 25 | |||
| Power supply slew rate during power-up | TSR_POWER_UP | 1 | 67 | V/ms | -40 °C ≤ TA ≤ 85 °C, all VDD | 25 | |
| External reset pulse width | TXRES | 5 | µs | -40 °C ≤ TA ≤ 85 °C, all VDD | 25 |
CAD (KiCad official)
- Symbol:
CY8CMBR3110-SX2IT - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cy8cmbr3110-sx2it-etched.step/cy8cmbr3110-sx2it-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8cmbr3110-sx2it.step/cy8cmbr3110-sx2it.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (42 pp, sha256
c922377abc0466b1, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).