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74VHCT00AFT
Public Made by Adomby adom
TOSHIBA Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdown74VHCT00AFT
TOSHIBA · Logic Gates · TSSOP-14
74VHCT00AFT from TOSHIBA, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 2 | 1B | input | Gate 1 input B; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 3 | 1Y | output | Gate 1 NAND output, 8 mA drive at VCC = 4.5 V (IOL = 8 mA, IOH = -8 mA). |
| 4 | 2A | input | Gate 2 input A; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 5 | 2B | input | Gate 2 input B; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 6 | 2Y | output | Gate 2 NAND output, 8 mA drive at VCC = 4.5 V (IOL = 8 mA, IOH = -8 mA). |
| 7 | GND | power_in | Ground pin (0 V reference). |
| 8 | 3Y | output | Gate 3 NAND output, 8 mA drive at VCC = 4.5 V (IOL = 8 mA, IOH = -8 mA). |
| 9 | 3A | input | Gate 3 input A; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 10 | 3B | input | Gate 3 input B; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 11 | 4Y | output | Gate 4 NAND output, 8 mA drive at VCC = 4.5 V (IOL = 8 mA, IOH = -8 mA). |
| 12 | 4A | input | Gate 4 input A; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 13 | 4B | input | Gate 4 input B; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max, and tolerates 0 to 5.5 V. |
| 14 | VCC | power_in | Supply voltage, operating range 4.5 to 5.5 V (absolute maximum -0.5 to 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 3 | ||
| Input diode current | IIK | -20 | mA | 3 | |||
| Output diode current | IOK | -20 | 20 | mA | 3 | ||
| Output current | IOUT | -25 | 25 | mA | 3 | ||
| VCC/ground current | ICC | -50 | 50 | mA | 3 | ||
| Power dissipation | PD | 180 | mW | Ta = -40 to 85 (Note 4); derate -3.25 mW/°C from 85 to 125 down to 50 mW | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Supply voltage (recommended operating) | VCC | 4.5 | 5.5 | V | 3 | ||
| Input voltage (operating) | VIN | 0 | 5.5 | V | 3 | ||
| Operating temperature | Topr | -40 | 125 | °C | 3 | ||
| Input rise and fall times | dt/dv | 0 | 20 | ns/V | 3 | ||
| High-level input voltage | VIH | 2 | V | Ta = 25 °C; VCC = 4.5 to 5.5 V | 4 | ||
| Low-level input voltage | VIL | 0.8 | V | Ta = 25 °C; VCC = 4.5 to 5.5 V | 4 | ||
| High-level output voltage (IOH = -50 µA) | VOH | 4.4 | 4.5 | V | Ta = 25 °C; VCC = 4.5 V; IOH = -50 µA | 4 | |
| High-level output voltage (IOH = -8 mA) | VOH | 3.94 | V | Ta = 25 °C; VCC = 4.5 V; IOH = -8 mA | 4 | ||
| Low-level output voltage (IOL = 50 µA) | VOL | 0 | 0.1 | V | Ta = 25 °C; VCC = 4.5 V; IOL = 50 µA | 4 | |
| Low-level output voltage (IOL = 8 mA) | VOL | 0.36 | V | Ta = 25 °C; VCC = 4.5 V; IOL = 8 mA | 4 | ||
| Input leakage current | IIN | -0.1 | 0.1 | µA | Ta = 25 °C; VIN = 5.5 V or GND | 4 | |
| Quiescent supply current | ICC | 2 | µA | Ta = 25 °C; VIN = VCC or GND | 4 | ||
| Quiescent supply current (per input VIN = 3.4 V) | ICCT | 1.35 | mA | Ta = 25 °C; per input VIN = 3.4 V; other input VCC or GND | 4 | ||
| Output leakage current (power-OFF) | IOPD | 0.5 | µA | Ta = 25 °C; VOUT = 5.5 V | 4 | ||
| High-level output voltage (IOH = -50 µA) | VOH | 4.4 | V | Ta = -40 to 85 °C; VCC = 4.5 V; IOH = -50 µA | 4 | ||
| High-level output voltage (IOH = -8 mA) | VOH | 3.8 | V | Ta = -40 to 85 °C; VCC = 4.5 V; IOH = -8 mA | 4 | ||
| Low-level output voltage (IOL = 50 µA) | VOL | 0.1 | V | Ta = -40 to 85 °C; VCC = 4.5 V; IOL = 50 µA | 4 | ||
| Low-level output voltage (IOL = 8 mA) | VOL | 0.44 | V | Ta = -40 to 85 °C; VCC = 4.5 V; IOL = 8 mA | 4 | ||
| Input leakage current | IIN | -1 | 1 | µA | Ta = -40 to 85 °C; VIN = 5.5 V or GND | 4 | |
| Quiescent supply current | ICC | 20 | µA | Ta = -40 to 85 °C; VIN = VCC or GND | 4 | ||
| Quiescent supply current (per input VIN = 3.4 V) | ICCT | 1.5 | mA | Ta = -40 to 85 °C; per input VIN = 3.4 V; other input VCC or GND | 4 | ||
| Output leakage current (power-OFF) | IOPD | 5 | µA | Ta = -40 to 85 °C; VOUT = 5.5 V | 4 | ||
| High-level output voltage (IOH = -8 mA) | VOH | 3.7 | V | Ta = -40 to 125 °C; VCC = 4.5 V; IOH = -8 mA | 4 | ||
| Low-level output voltage (IOL = 8 mA) | VOL | 0.55 | V | Ta = -40 to 125 °C; VCC = 4.5 V; IOL = 8 mA | 4 | ||
| Input leakage current | IIN | -2 | 2 | µA | Ta = -40 to 125 °C; VIN = 5.5 V or GND | 4 | |
| Quiescent supply current | ICC | 40 | µA | Ta = -40 to 125 °C; VIN = VCC or GND | 4 | ||
| Output leakage current (power-OFF) | IOPD | 20 | µA | Ta = -40 to 125 °C; VOUT = 5.5 V | 4 | ||
| Propagation delay time (CL = 15 pF) | tPLH,tPHL | 5 | 6.9 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; input tr = tf = 3 ns | 5 | |
| Propagation delay time (CL = 50 pF) | tPLH,tPHL | 5.54 | 7.9 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; input tr = tf = 3 ns | 5 | |
| Input capacitance | CIN | 10 | pF | Ta = 25 °C; input tr = tf = 3 ns | 5 | ||
| Propagation delay time (CL = 15 pF) | tPLH,tPHL | 1 | 8 | ns | Ta = -40 to 85 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; input tr = tf = 3 ns | 5 | |
| Propagation delay time (CL = 50 pF) | tPLH,tPHL | 1 | 9 | ns | Ta = -40 to 85 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; input tr = tf = 3 ns | 5 | |
| Propagation delay time (CL = 15 pF) | tPLH,tPHL | 1 | 9 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; input tr = tf = 3 ns | 5 | |
| Propagation delay time (CL = 50 pF) | tPLH,tPHL | 1 | 10 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; input tr = tf = 3 ns | 5 | |
| Quiet output maximum dynamic VOL | VOLP | 0.4 | 0.8 | V | Ta = 25 °C; VCC = 5.0 V; CL = 50 pF; input tr = tf = 3 ns | 5 | |
| Quiet output minimum dynamic VOL | VOLV | -0.8 | -0.4 | V | Ta = 25 °C; VCC = 5.0 V; CL = 50 pF; input tr = tf = 3 ns | 5 | |
| Minimum high-level dynamic input voltage | VIHD | 2 | V | Ta = 25 °C; VCC = 5.0 V; CL = 50 pF; input tr = tf = 3 ns | 5 | ||
| Maximum low-level dynamic input voltage | VILD | 0.8 | V | Ta = 25 °C; VCC = 5.0 V; CL = 50 pF; input tr = tf = 3 ns | 5 |
CAD (KiCad official)
- Symbol:
74VHCT00AFT - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74vhct00aft-etched.step/74vhct00aft-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74vhct00aft.step/74vhct00aft.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (7 pp, sha256
4db6699a18233293, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).