CYUSB3065-BZXI from Cypress Semicon, in a BGA-121. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
A1	U3VSSQ	power_in	USB 3.0 ground return for the 1.2 V SuperSpeed supply domain.
A2	U3RXVDDQ	power_in	USB 3.0 1.2 V receive supply rated 1.15 V to 1.25 V (1.2 V typical), requiring a 22 µF bypass capacitor.
A3	SSRXM	input	USB 3.0 SuperSpeed receive differential input with internal ESD protection up to ±2.2 kV HBM.
A4	SSRXP	input	USB 3.0 SuperSpeed receive differential input with internal ESD protection up to ±2.2 kV HBM.
A5	SSTXP	output	USB 3.0 SuperSpeed transmit differential output with internal ESD protection up to ±2.2 kV HBM.
A6	SSTXM	output	USB 3.0 SuperSpeed transmit differential output with internal ESD protection up to ±2.2 kV HBM.
A7	AVDD	power_in	Analog supply rated 1.15 V to 1.25 V (1.2 V typical).
A8	VSS	power_in	Ground connection.
A9	DP	bidirectional	USB 2.0 D+ data line with built-in ESD protection on the USB interface (VUSB power domain).
A10	DM	bidirectional	USB 2.0 D- data line with built-in ESD protection on the USB interface (VUSB power domain).
A11	GPIO[24]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
B1	VDDIO3	power_in	SPI/I2S power domain supply rated 1.7 V to 3.6 V.
B2	VSS	power_in	Ground connection.
B3	GPIO[23]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
B4	GPIO[21]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
B5	U3TXVDDQ	power_in	USB 3.0 1.2 V transmit supply rated 1.15 V to 1.25 V (1.2 V typical), requiring a 22 µF bypass capacitor.
B6	CVDDQ	power_in	Clock voltage supply rated 1.7 V to 3.6 V (1.8 V or 3.3 V typical).
B7	AVSS	power_in	Analog ground connection.
B8	VSS	power_in	Ground connection.
B9	VSS	power_in	Ground connection.
B10	VDD	power_in	Core supply rated 1.15 V to 1.25 V (1.2 V typical); absolute maximum 1.25 V.
B11	TRST#	input	JTAG test reset input with a fixed internal 50 kΩ pull-up.
C1	SPI_SSN / GPIO[54]	bidirectional	SPI slave select, also usable as general-purpose I/O, in the VDDIO3 power domain.
C2	SPI_MISO / GPIO[55]	bidirectional	SPI master-in/slave-out, also usable as general-purpose I/O, in the VDDIO3 power domain.
C3	VDD	power_in	Core supply rated 1.15 V to 1.25 V (1.2 V typical); absolute maximum 1.25 V.
C4	GPIO[26]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
C5	RESET#	input	Device reset input; assertion of RESET# is the exit method from core power-down mode.
C6	GPIO[18]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
C7	GPIO[19]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
C8	GPIO[22]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
C9	GPIO[45]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
C10	TDO	output	JTAG test data output in the VDDIO1 power domain.
C11	I2S_MCLK / GPIO[57]	bidirectional	I2S master clock, also usable as general-purpose I/O, in the VDDIO3 power domain.
D1	I2S_CLK / GPIO[50]	bidirectional	I2S clock, also usable as general-purpose I/O, in the VDDIO2 power domain.
D2	I2S_SD / GPIO[51]	bidirectional	I2S serial data, also usable as general-purpose I/O, in the VDDIO2 power domain.
D3	I2S_WS / GPIO[52]	bidirectional	I2S word select, also usable as general-purpose I/O, in the VDDIO2 power domain.
D4	SPI_SCK / GPIO[53]	bidirectional	SPI serial clock, also usable as general-purpose I/O, in the VDDIO3 power domain.
D5	SPI_MOSI / GPIO[56]	bidirectional	SPI master-out/slave-in, also usable as general-purpose I/O, in the VDDIO3 power domain.
D6	CLKIN_32	input	32-kHz watchdog timer clock input.
D7	CLKIN	input	Main clock input in the CVDDQ power domain.
D8	VSS	power_in	Ground connection.
D9	I2C_SCL	bidirectional	I2C serial clock in the VDDIO1 power domain (1.7 V to 3.6 V).
D10	I2C_SDA	bidirectional	I2C serial data in the VDDIO1 power domain (1.7 V to 3.6 V).
D11	GPIO[17]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
E1	UART_CTS / GPIO[47]	bidirectional	UART clear-to-send, also usable as general-purpose I/O, in the VDDIO2 power domain.
E2	VSS	power_in	Ground connection.
E3	VDDIO2	power_in	UART/I2S power supply domain rated 1.7 V to 3.6 V (1.8, 2.5, 3.3 V typical).
E4	UART_RX / GPIO[49]	bidirectional	UART receive, also usable as general-purpose I/O, in the VDDIO2 power domain.
E5	UART_TX / GPIO[48]	bidirectional	UART transmit, also usable as general-purpose I/O, in the VDDIO2 power domain.
E6	GPIO[20]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
E7	TDI	input	JTAG test data input with a fixed internal 50 kΩ pull-up.
E8	TMS	input	JTAG test mode select input with a fixed internal 50 kΩ pull-up.
E9	VDD	power_in	Core supply rated 1.15 V to 1.25 V (1.2 V typical); absolute maximum 1.25 V.
E10	VUSB	power_in	USB voltage supply rated 4 V to 6 V (5 V typical).
E11	VSS	power_in	Ground connection.
F1	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
F2	REFCLK	input	Reference clock input in the VDDIO1 power domain.
F3	GPIO[44]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
F4	XRST	output	Output signal XRST in the VDDIO1 power domain; no further function is stated in the provided text.
F5	UART_RTS / GPIO[46]	bidirectional	UART request-to-send, also usable as general-purpose I/O, in the VDDIO2 power domain.
F6	TCK	input	JTAG test clock input with a fixed internal 10 kΩ pull-down.
F7	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
F8	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
F9	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
F10	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
F11	VDD	power_in	Core supply rated 1.15 V to 1.25 V (1.2 V typical); absolute maximum 1.25 V.
G1	VSS	power_in	Ground connection.
G2	XSHUTDOWN	output	Output signal XSHUTDOWN in the VDDIO1 power domain; no further function is stated in the provided text.
G3	MCLK	output	Output clock MCLK in the VDDIO1 power domain; no further function is stated in the provided text.
G4	PMODE[0] / GPIO[30]	bidirectional	Power-mode configuration pin, also usable as general-purpose I/O, in the VDDIO1 power domain.
G5	GPIO[25]	bidirectional	General-purpose I/O with firmware-selectable internal 50 kΩ pull-up or 10 kΩ pull-down and support for up to 16 pF external load.
G6	HSYNC_test	bidirectional	Test pin HSYNC_test listed as I/O in the VDDIO1 power domain.
G7	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
G8	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
G9	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
G10	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
G11	VSS	power_in	Ground connection.
H1	VDD	power_in	Core supply rated 1.15 V to 1.25 V (1.2 V typical); absolute maximum 1.25 V.
H2	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
H3	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
H4	PMODE[1] / GPIO[31]	bidirectional	Power-mode configuration pin, also usable as general-purpose I/O, in the VDDIO1 power domain.
H5	VSYNC_test	bidirectional	Test pin VSYNC_test listed as I/O in the VDDIO1 power domain.
H6	MIPI RESET	bidirectional	MIPI-related reset pin listed as I/O in the VDDIO1 power domain.
H7	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
H8	PCLK_test	bidirectional	Test pin PCLK_test listed as I/O in the VDDIO1 power domain.
H9	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
H10	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
H11	VDDIO1	power_in	I2C, JTAG and GPIO power domain rated 1.7 V to 3.6 V (1.8, 2.5, 3.3 V typical).
J1	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
J2	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
J3	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
J4	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
J5	MIPI_D0P	input	MIPI CSI-2 receive data lane 0 positive differential input; unused MIPI input data lanes must be connected to GND.
J6	MIPI_D1P	input	MIPI CSI-2 receive data lane 1 positive differential input; unused MIPI input data lanes must be connected to GND.
J7	MIPI_CP	input	MIPI CSI-2 clock lane positive differential input in the VDD_MIPI power domain.
J8	MIPI_D2P	input	MIPI CSI-2 receive data lane 2 positive differential input; unused MIPI input data lanes must be connected to GND.
J9	MIPI_D2N	input	MIPI CSI-2 receive data lane 2 negative differential input; present on CYUSB3065 and not available on CYUSB3064.
J10	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
J11	VDD	power_in	Core supply rated 1.15 V to 1.25 V (1.2 V typical); absolute maximum 1.25 V.
K1	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
K2	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
K3	VSS	power_in	Ground connection.
K4	VSS	power_in	Ground connection.
K5	MIPI_D0N	input	MIPI CSI-2 receive data lane 0 negative differential input; unused MIPI input data lanes must be connected to GND.
K6	MIPI_D1N	input	MIPI CSI-2 receive data lane 1 negative differential input; unused MIPI input data lanes must be connected to GND.
K7	MIPI_CN	input	MIPI CSI-2 clock lane negative differential input in the VDD_MIPI power domain.
K8	MIPI_D3N	input	MIPI CSI-2 receive data lane 3 negative differential input; present on CYUSB3065 and not available on CYUSB3064.
K9	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
K10	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
K11	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
L1	VSS	power_in	Ground connection.
L2	VSS	power_in	Ground connection.
L3	VSS	power_in	Ground connection.
L4	PMODE[2] / GPIO[32]	bidirectional	Power-mode configuration pin, also usable as general-purpose I/O, in the VDDIO1 power domain.
L5	VDD_MIPI	power_in	MIPI bridge D-PHY supply rated 1.15 V to 1.25 V (1.2 V typical).
L6	VSS	power_in	Ground connection.
L7	VDD	power_in	Core supply rated 1.15 V to 1.25 V (1.2 V typical); absolute maximum 1.25 V.
L8	MIPI_D3P	input	MIPI CSI-2 receive data lane 3 positive differential input; present on CYUSB3065 and not available on CYUSB3064.
L9	VDDIO1	power_in	I2C, JTAG and GPIO power domain rated 1.7 V to 3.6 V (1.8, 2.5, 3.3 V typical).
L10	DNU	unconnected	Marked DNU (do not use) in the ball map and pin list; no function is specified.
L11	VSS	power_in	Ground connection.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	BGA-121
Category	Interface ICs
Pins	121

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage temperature		-65		150	°C		17
Supply voltage to ground potential VDD, AVDDQ	VDD, AVDDQ			1.25	V		17
Supply voltage to ground potential VDDIO1, VDDIO2, VDDIO3	VDDIO1, VDDIO2, VDDIO3			3.6	V		17
Supply voltage to ground potential U3TXVDDQ, U3RXVDDQ	U3TXVDDQ, U3RXVDDQ			1.25	V		17
Maximum latch-up current				140	mA		17
Maximum output short-circuit current for all I/O configurations				-100	mA	VOUT = 0 V	17
TA (ambient temperature under bias) Industrial	TA	-40		85	°C	Industrial grade	17
Supply voltage VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ	VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ	1.15		1.25	V		17
VUSB supply voltage	VUSB	4		6	V		17
Supply voltage VDDIO1, VDDIO2, VDDIO3, CVDDQ	VDDIO1, VDDIO2, VDDIO3, CVDDQ	1.7		3.6	V		17
Core voltage supply	VDD	1.15		1.25	V	1.2-V typical	18
Analog voltage supply	AVDD	1.15		1.25	V	1.2-V typical	18
MIPI bridge D-PHY supply voltage	VDD_MIPI	1.15		1.25	V	1.2-V typical	18
I2C, JTAG and GPIO power domain	VDDIO1	1.7		3.6	V	1.8-, 2.5-, and 3.3-V typical	18
UART/I2S power supply domain	VDDIO2	1.7		3.6	V	1.8-, 2.5-, and 3.3-V typical	18
SPI/I2S power supply domain	VDDIO3	1.7		3.6	V	1.8-, 2.5-, and 3.3-V typical	18
USB voltage supply	VUSB	4		6	V	5-V typical	18
USB 3.0 1.2-V supply	U3TXVDDQ	1.15		1.25	V	1.2-V typical	18
Clock voltage supply	CVDDQ	1.7		3.6	V	1.8-, 3.3-V typical	18
Input leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM	IIX	-1		1	µA	All I/O signals held at VDDQ	18
Output High-Z leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM and MIPI CSI-2 signals	IOZ	-1		1	µA	All I/O signals held at VDDQ	18
Core and analog voltage operating current	ICC			192	mA	Total current through AVDD, VDD	18
USB voltage supply operating current	ICC USB			60	mA		18
Total suspend current during suspend mode with USB 3.0 PHY enabled (Core)	ISB1			558.35	µA	Core current measured through VDD, AVDD and VDD_MIPI	18
Total standby current during core power-down mode (Core)	ISB3			148.31	µA	Core current measured through VDD, AVDD and VDD_MIPI	18
Voltage ramp rate on core and I/O supplies	VRAMP	0.2		12	V/ms	Voltage ramp must be monotonic	18
Noise level permitted on VDD and I/O supplies	VN			100	mV	Max p-p noise level permitted on all supplies except AVDD	18
Noise level permitted on AVDD supply	VN_AVDD			20	mV	Max p-p noise level permitted on AVDD	18
Pin signal voltage range	VPIN	-50		1350	mV		19
Logic 1 input voltage	VIH	880			mV		19
Logic 0 input voltage	VIL			550	mV		19
Common-mode voltage HS receiver mode	VCMRX (DC)	70		330	mV	HS receiver mode	19
Differential input high threshold	VIDTH			70	mV		19
Differential input low threshold	VIDTL	-70			mV		19
Single-ended input high voltage	VIHHS			460	mV		19
Single-ended input low voltage	VILHS	-40			mV		19
Data to clock skew measured at the transmitter	TSKEW	-0.15		0.15	UIINST		20
Data to clock setup time at receiver	TSETUP	0.15			UIINST		20
Clock to data hold time at receiver	THOLD	0.15			UIINST		20
One data bit time (instantaneous)	UIINST	1		12.5	ns		20
Period of dual data rate clock	TCLKp	2		25	ns		20
Reference clock frequency	RefClk	6		40	MHz		20
Duty cycle	RefclkDutyCyl	40		60	%		20
Reference clock input period jitter	RefClkPJ	-100		100	ps		20
Input noise rejection	eSPIKE			300	V.ps	Spike above VIL in LP-0 or below VIH in LP-1 state	21
Minimum pulse width response	TMIN-RX	20			ns		21
Length of any low power state period	TLPX	50			ns		21
Interference frequency	FINT	450			MHz		21
Common-mode interference beyond 450 MHz	ΔVCMRX(HF)			100	mV	Peak amplitude of sine wave superimposed on receiver inputs	21
Common-mode interference beyond 50-450 MHz	ΔVCMRX(LF)	-50		50	mV	Excluding static ground shift of 50 mV	21
SCL clock frequency	fSCL	0		100	kHz	I2C Standard Mode Parameters	22
Data setup time	tSU:DAT	250			ns	I2C Standard Mode Parameters	22
Rise time of both SDA and SCL signals	tr			1000	ns	I2C Standard Mode Parameters	22
Fall time of both SDA and SCL signals	tf			300	ns	I2C Standard Mode Parameters	22
Data valid time	tVD:DAT			3.45	µs	I2C Standard Mode Parameters	22
Maximum Junction Temperature	TJ MAX			125	°C		19
Thermal resistance (junction to ambient)	JA		24.4		°C/W		19
Thermal resistance (junction to board)	JB		17.27		°C/W		19
Thermal resistance (junction to case)	JC		5.5		°C/W		19

CAD (KiCad official)

Symbol: CYUSB3065-BZXI
Footprint: Package_BGA:BGA-121_9.0x9.0mm_Layout11x11_P0.8mm_Ball0.4mm_Pad0.35mm_NSMD
3D model: BGA-121 (KiCad packages3D, STEP)
3D model files: cyusb3065-bzxi-etched.step / cyusb3065-bzxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cyusb3065-bzxi.step / cyusb3065-bzxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (41 pp, sha256 a6a4050370e884f7, retrieved 2026-11-02, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CYUSB3065-BZXI

Changed since verified CYUSB3065-BZXI

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README