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STM32F413RGT6

Public Made by Adom

by adom

STMicroelectronics Global Sourcing Parts, LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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STM32F413RGT6

STMicroelectronics · Global Sourcing Parts · LQFP-64(10x10)

STM32F413RGT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply input for the RTC and backup registers.
2 PC13-ANTI_TAMP bidirectional 5 V tolerant I/O supplied through a power switch that sinks only 3 mA, so output speed is limited to 2 MHz at 30 pF maximum load and it must not be used as a current source; additional function TAMP_1.
3 PC14-OSC32_IN bidirectional 5 V tolerant I/O (except in oscillator mode) supplied through the 3 mA power switch, so output use is limited to 2 MHz at 30 pF and it must not source current; additional function OSC32_IN.
4 PC15-OSC32_OUT bidirectional 5 V tolerant I/O (except in oscillator mode) supplied through the 3 mA power switch, so output use is limited to 2 MHz at 30 pF and it must not source current; additional function OSC32_OUT.
5 PH0-OSC_IN bidirectional 5 V tolerant except in oscillator mode; additional function OSC_IN (4-26 MHz HSE oscillator input).
6 PH1-OSC_OUT bidirectional 5 V tolerant except in oscillator mode; additional function OSC_OUT (4-26 MHz HSE oscillator output).
7 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
8 PC0 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_IN1, DFSDM2_CKIN4, SAI1_MCLK_B and EVENTOUT; additional functions ADC1_IN10 and WKUP2.
9 PC1 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_OUT, DFSDM2_DATIN4, SAI1_SD_B and EVENTOUT; additional functions ADC1_IN11 and WKUP3.
10 PC2 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_IN2, DFSDM2_DATIN7, SPI2_MISO, I2S2ext_SD, SAI1_SCK_B, DFSDM1_CKOUT, FSMC_NWE and EVENTOUT; additional function ADC1_IN12.
11 PC3 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_ETR, DFSDM2_CKIN7, SPI2_MOSI/I2S2_SD, SAI1_FS_B, FSMC_A0 and EVENTOUT; additional function ADC1_IN13.
12 VSSA power_in Analog ground pin.
13 VDDA power_in Analog supply pin.
14 PA0 bidirectional 5 V tolerant I/O with alternate functions TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX and EVENTOUT; additional functions ADC1_IN0 and WKUP1.
15 PA1 bidirectional 5 V tolerant I/O with alternate functions TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3 and EVENTOUT; additional function ADC1_IN1.
16 PA2 bidirectional 5 V tolerant I/O with alternate functions TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, FSMC_D4/FSMC_DA4 and EVENTOUT; additional function ADC1_IN2.
17 PA3 bidirectional 5 V tolerant I/O with alternate functions TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, SAI1_SD_B, FSMC_D5/FSMC_DA5 and EVENTOUT; additional function ADC1_IN3.
18 VSS power_in Ground pin.
19 VDD power_in Digital supply pin; application supply range is 1.7 to 3.6 V.
20 PA4 bidirectional 3.3 V tolerant I/O directly connected to DAC with alternate functions SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, DFSDM1_DATIN1, FSMC_D6/FSMC_DA6 and EVENTOUT; additional functions ADC1_IN4 and DAC_OUT1.
21 PA5 bidirectional 3.3 V tolerant I/O directly connected to DAC with alternate functions TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, DFSDM1_CKIN1, FSMC_D7/FSMC_DA7 and EVENTOUT; additional functions ADC1_IN5 and DAC_OUT2.
22 PA6 bidirectional 5 V tolerant I/O with alternate functions TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, DFSDM2_CKIN1, TIM13_CH1, QUADSPI_BK2_IO0, SDIO_CMD and EVENTOUT; additional function ADC1_IN6.
23 PA7 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, DFSDM2_DATIN1, TIM14_CH1, QUADSPI_BK2_IO1 and EVENTOUT; additional function ADC1_IN7.
24 PC4 bidirectional 5 V tolerant I/O with alternate functions DFSDM2_CKIN2, I2S1_MCK, QUADSPI_BK2_IO2, FSMC_NE4 and EVENTOUT; additional function ADC1_IN14.
25 PC5 bidirectional 5 V tolerant I/O with alternate functions DFSDM2_DATIN2, I2CFMP1_SMBA, USART3_RX, QUADSPI_BK2_IO3, FSMC_NOE and EVENTOUT; additional function ADC1_IN15.
26 PB0 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI5_SCK/I2S5_CK and EVENTOUT; additional function ADC1_IN8.
27 PB1 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI5_NSS/I2S5_WS, DFSDM1_DATIN0, QUADSPI_CLK and EVENTOUT; additional function ADC1_IN9.
28 PB2 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_OUT, DFSDM1_CKIN0, QUADSPI_CLK and EVENTOUT; additional function BOOT1.
29 PB10 bidirectional 5 V tolerant I/O with I2C FM+ option and alternate functions TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, USART3_TX, I2CFMP1_SCL, DFSDM2_CKOUT, SDIO_D7 and EVENTOUT.
30 VCAP_1 power_in Internal voltage regulator output pin that requires an external VCAP_1/VCAP_2 capacitor as described in section 6.3.2.
31 VSS power_in Ground pin.
32 VDD power_in Digital supply pin; application supply range is 1.7 to 3.6 V.
33 PB12 bidirectional 5 V tolerant I/O with alternate functions TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, SPI3_SCK/I2S3_CK, USART3_CK, CAN2_RX, DFSDM1_DATIN1, UART5_RX, FSMC_D13/FSMC_DA13 and EVENTOUT.
34 PB13 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH1N, I2CFMP1_SMBA, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, USART3_CTS, CAN2_TX, DFSDM1_CKIN1, UART5_TX and EVENTOUT.
35 PB14 bidirectional 5 V tolerant I/O with I2C FM+ option and alternate functions TIM1_CH2N, TIM8_CH2N, I2CFMP1_SDA, SPI2_MISO, I2S2ext_SD, USART3_RTS, DFSDM1_DATIN2, TIM12_CH1, FSMC_D0/FSMC_DA0, SDIO_D6 and EVENTOUT.
36 PB15 bidirectional 5 V tolerant I/O with I2C FM+ option and alternate functions RTC_REFIN, TIM1_CH3N, TIM8_CH3N, I2CFMP1_SCL, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, TIM12_CH2, SDIO_CK and EVENTOUT.
37 PC6 bidirectional 5 V tolerant I/O with I2C FM+ option and alternate functions TIM3_CH1, TIM8_CH1, I2CFMP1_SCL, I2S2_MCK, DFSDM1_CKIN3, DFSDM2_DATIN6, USART6_TX, FSMC_D1/FSMC_DA1, SDIO_D6 and EVENTOUT.
38 PC7 bidirectional 5 V tolerant I/O with I2C FM+ option and alternate functions TIM3_CH2, TIM8_CH2, I2CFMP1_SDA, SPI2_SCK/I2S2_CK, I2S3_MCK, DFSDM2_CKIN6, USART6_RX, DFSDM1_DATIN3, SDIO_D7 and EVENTOUT.
39 PC8 bidirectional 5 V tolerant I/O with alternate functions TIM3_CH3, TIM8_CH3, DFSDM2_CKIN3, USART6_CK, QUADSPI_BK1_IO2, SDIO_D0 and EVENTOUT.
40 PC9 bidirectional 5 V tolerant I/O with alternate functions MCO_2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S2_CKIN, DFSDM2_DATIN3, QUADSPI_BK1_IO0, SDIO_D1 and EVENTOUT.
41 PA8 bidirectional 5 V tolerant I/O with alternate functions MCO_1, TIM1_CH1, I2C3_SCL, DFSDM1_CKOUT, USART1_CK, UART7_RX, USB_FS_SOF, CAN3_RX, SDIO_D1 and EVENTOUT.
42 PA9 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH2, DFSDM2_CKIN3, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, USB_FS_VBUS, SDIO_D2 and EVENTOUT.
43 PA10 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH3, DFSDM2_DATIN3, SPI2_MOSI/I2S2_SD, SPI5_MOSI/I2S5_SD, USART1_RX, USB_FS_ID and EVENTOUT.
44 PA11 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH4, DFSDM2_CKIN5, SPI2_NSS/I2S2_WS, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, USB_FS_DM, UART4_RX and EVENTOUT.
45 PA12 bidirectional 5 V tolerant I/O with alternate functions TIM1_ETR, DFSDM2_DATIN5, SPI2_MISO, SPI5_MISO, USART1_RTS, USART6_RX, CAN1_TX, USB_FS_DP, UART4_TX and EVENTOUT.
46 PA13 bidirectional 5 V tolerant I/O with alternate function JTMS-SWDIO and EVENTOUT.
47 VSS power_in Ground pin.
48 VDD power_in Digital supply pin; application supply range is 1.7 to 3.6 V.
49 PA14 bidirectional 5 V tolerant I/O with alternate function JTCK-SWCLK and EVENTOUT.
50 PA15 bidirectional 5 V tolerant I/O with alternate functions JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART1_TX, UART7_TX, SAI1_MCLK_A, CAN3_TX and EVENTOUT.
51 PC10 bidirectional 5 V tolerant I/O with alternate functions DFSDM2_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, QUADSPI_BK1_IO1, SDIO_D2 and EVENTOUT.
52 PC11 bidirectional 5 V tolerant I/O with alternate functions DFSDM2_DATIN5, I2S3ext_SD, SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, FSMC_D2/FSMC_DA2, SDIO_D3 and EVENTOUT.
53 PC12 bidirectional 5 V tolerant I/O with alternate functions SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, FSMC_D3/FSMC_DA3, SDIO_CK and EVENTOUT.
54 PD2 bidirectional 5 V tolerant I/O with alternate functions TIM3_ETR, DFSDM2_CKOUT, UART5_RX, FSMC_NWE, SDIO_CMD and EVENTOUT.
55 PB3 bidirectional 5 V tolerant I/O with I2C FM+ option and alternate functions JTDO-SWO, TIM2_CH2, I2CFMP1_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX, UART7_RX, I2C2_SDA, SAI1_SD_A, CAN3_RX and EVENTOUT.
56 PB4 bidirectional 5 V tolerant I/O with alternate functions JTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, UART7_TX, I2C3_SDA, SAI1_SCK_A, CAN3_TX, SDIO_D0 and EVENTOUT.
57 PB5 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, SAI1_FS_A, UART5_RX, SDIO_D3 and EVENTOUT.
58 PB6 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_ETR, TIM4_CH1, I2C1_SCL, DFSDM2_CKIN7, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, UART5_TX, SDIO_D0 and EVENTOUT.
59 PB7 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_IN2, TIM4_CH2, I2C1_SDA, DFSDM2_DATIN7, USART1_RX, FSMC_NL and EVENTOUT.
60 BOOT0 input Dedicated BOOT0 pin (listed as VPP in Table 10).
61 PB8 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_OUT, TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, DFSDM2_CKIN1, CAN1_RX, I2C3_SDA, UART5_RX, SDIO_D4 and EVENTOUT.
62 PB9 bidirectional 5 V tolerant I/O with alternate functions TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, DFSDM2_DATIN1, CAN1_TX, I2C2_SDA, UART5_TX, SDIO_D5 and EVENTOUT.
63 VSS power_in Ground pin.
64 VDD power_in Digital supply pin; application supply range is 1.7 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Global Sourcing Parts
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (including VDDA, VDD, VDDUSB and VBAT) VDD-VSS -0.3 4 V 80
Input voltage on FT and TC pins VIN -0.3 V 80
Input voltage on TTa pins VIN -0.3 4 V 80
Input voltage on any other pin VIN -0.3 4 V 80
Input voltage for BOOT0 VIN 0 9 V 80
Variations between different VDD power pins /ΔVDDx/ 50 mV 80
Variations between all the different ground pins including VREF- /VSSX −VSS/ 50 mV 80
Total current into sum of all VDD_x power lines (source) ΣIVDD 180 mA 81
Total current out of sum of all VSS_x ground lines (sink) Σ IVSS -180 mA 81
Total current into VDDUSB power lines (source) Σ IVDDUSB 25 mA 81
Maximum current into each VDD_x power line (source) IVDD 100 mA 81
Maximum current out of each VSS_x ground line (sink) IVSS -100 mA 81
Output current sunk by any I/O and control pin IIO 25 mA 81
Output current sourced by any I/O and control pin IIO -25 mA 81
Total output current sunk by sum of all I/O and control pins ΣIIO 120 mA 81
Total output current sunk by sum of all USB I/Os ΣIIO 25 mA 81
Total output current sourced by sum of all I/Os and control pins ΣIIO -120 mA 81
Injected current on FT and TC pins IINJ(PIN) -5 0 mA 81
Injected current on TTa pins IINJ(PIN) -5 5 mA 81
Total injected current (sum of all I/O and control pins) ΣIINJ(PIN) -25 25 mA 81
Storage temperature range TSTG -65 150 °C 81
Maximum junction temperature TJ 125 °C 81
Internal AHB clock frequency, Power Scale3 fHCLK 0 64 MHz Regulator ON, VOS[1:0] = 0x01 82
Internal AHB clock frequency, Power Scale2 fHCLK 0 84 MHz Regulator ON, VOS[1:0] = 0x10 82
Internal AHB clock frequency, Power Scale1 fHCLK 0 100 MHz Regulator ON, VOS[1:0] = 0x11 82
Internal APB1 clock frequency fPCLK1 0 50 MHz 82
Internal APB2 clock frequency fPCLK2 0 100 MHz 82
Standard operating voltage VDD 1.7 3.6 V 82
Analog operating voltage (ADC limited to 1.2 M samples) VDDA 1.7 2.4 V ADC limited to 1.2 M samples; must be same potential as VDD 82
Analog operating voltage (ADC limited to 2.4 M samples) VDDA 2.4 3.6 V ADC limited to 2.4 M samples 82
USB supply voltage (supply voltage for PA11 and PA12 pins) VDDUSB 1.7 3.3 3.6 V USB not used 82
USB supply voltage (supply voltage for PA11 and PA12 pins) VDDUSB 3 3.6 V USB used 82
Backup operating voltage VBAT 1.65 3.6 V 82
Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins V12 1.08 1.14 1.2 V VOS[1:0] = 0x01, max frequency 64 MHz 82
Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins V12 1.2 1.26 1.32 V VOS[1:0] = 0x10, max frequency 84 MHz 82
Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins V12 1.26 1.32 1.38 V VOS[1:0] = 0x11, max frequency 100 MHz 82
Regulator OFF: 1.2 V external voltage on VCAP_1/VCAP_2 pins V12 1.1 1.14 1.2 V Max frequency 64 MHz 82
Regulator OFF: 1.2 V external voltage on VCAP_1/VCAP_2 pins V12 1.2 1.26 1.32 V Max frequency 84 MHz 82
Regulator OFF: 1.2 V external voltage on VCAP_1/VCAP_2 pins V12 1.26 1.32 1.38 V Max frequency 100 MHz 82
Input voltage on RST, FT and TC pins VIN -0.3 5.5 V 2 V ≤ VDD ≤ 3.6 V 83
Input voltage on RST, FT and TC pins VIN -0.3 5.2 V VDD ≤ 2 V 83
Input voltage on TTa pins VIN -0.3 V 83
Input voltage on BOOT0 pin VIN 0 9 V 83
Power dissipation at TA = 85 °C for range 6, LQFP64 PD 426 mW TA = 85 °C for range 6 83
Ambient temperature for range 6, maximum power dissipation TA -40 85 °C Range 6, maximum power dissipation 83
Ambient temperature for range 6, low power dissipation TA -40 105 °C Range 6, low power dissipation 83
Junction temperature range, range 6 TJ -40 105 °C Range 6 83
POR/PDR power-on/power-down reset threshold, falling edge VPOR/PDR 1.6 1.68 1.76 V Falling edge 86
POR/PDR power-on/power-down reset threshold, rising edge VPOR/PDR 1.64 1.72 1.8 V Rising edge 86
PDR hysteresis VPDRhyst 40 mV 86
BOR hysteresis VBORhyst 100 mV 86
PVD hysteresis VPVDhyst 100 mV 86
POR reset timing TRSTTEMPO 0.5 1.5 3 ms 87
In-Rush energy on voltage regulator power-on (POR or wakeup from Standby) ERUSH 5.4 µC VDD = 1.7 V, TA = 125 °C, IRUSH = 171 mA for 31 µs 87
LSI frequency fLSI 16.1 32 47 kHz VDD = 3 V, TA = -40 to 125 °C 113
LSI oscillator startup time tsu(LSI) 15 40 µs 113
LSI oscillator power consumption IDD(LSI) 0.4 0.6 µA 113
Stop mode supply current, Flash in Stop mode, low power regulator usage IDD_STOP 42.3 80.1 µA VDD = 1.7 V, all oscillators OFF, no IWDG, TA = 25 °C 98
Standby mode supply current, RTC and LSE OFF IDD_STBY 2.5 4 µA VDD = 3.6 V, TA = 25 °C 99
Supply current in Run mode, external clock PLL ON, all peripherals enabled, running from SRAM IDD 33.3 35.32 mA VDD = 3.6 V, fHCLK = 100 MHz, ART accelerator disabled, TA = 25 °C 89

CAD (KiCad official)

  • Symbol: STM32F413RGT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f413rgt6-etched.step / stm32f413rgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f413rgt6.step / stm32f413rgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (208 pp, sha256 f6011311b70d14ef, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF