AD5235BRUZ25 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLK	input	Serial input register clock that shifts in one bit at a time on positive clock edges.
2	SDI	input	Serial data input that shifts in one bit at a time on positive CLK edges, with the MSB loaded first.
3	SDO	output	Serial data output for readback and daisy-chaining, delayed by 24 or 25 clock pulses, and a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed whenever SDO is used.
4	GND	power_in	Ground pin that serves as the logic ground reference.
5	VSS	power_in	Negative supply that connects to 0 V for single-supply operation and must sink 2 mA for 15 ms when storing data to EEMEM in dual-supply use.
6	A1	passive	Terminal A of RDAC1.
7	W1	passive	Wiper terminal of RDAC1, with ADDR (RDAC1) = 0x0.
8	B1	passive	Terminal B of RDAC1.
9	B2	passive	Terminal B of RDAC2.
10	W2	passive	Wiper terminal of RDAC2, with ADDR (RDAC2) = 0x1.
11	A2	passive	Terminal A of RDAC2.
12	VDD	power_in	Positive power supply.
13	WP	input	Optional active-low write protect that prevents any change to present contents except the PR strobe, and it must be tied to VDD if not used.
14	PR	input	Optional hardware override preset that refreshes the scratchpad register from EEMEM on a logic high transition, and it must be tied to VDD if not used.
15	CS	input	Active-low serial register chip select, where serial register operation takes place when CS returns to logic high.
16	RDY	output	Active-high open-drain ready output that identifies completion of Instruction 2, 3, 8, 9, 10, and PR.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	ADC/DAC/Data Conversion
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Nominal Resistor Tolerance	ΔRAB/RAB	-8		8	%		4
Nominal Resistance Match	RAB1/RAB2	-0.1		0.1	%		4
Resistor Differential Nonlinearity	R-DNL	-1		1	LSB	RWB	4
Resistor Integral Nonlinearity	R-INL	-2		2	LSB	RWB	4
Wiper Resistance	RW		30	60	Ω	IW = 1 V/RWB, code = midscale, VDD = 5 V	4
Differential Nonlinearity	DNL	-1		1	LSB		4
Integral Nonlinearity	INL	-1		1	LSB		4
Full-Scale Error	VWFSE	-6		0	LSB	Code = full scale	4
Zero-Scale Error	VWZSE	0		4	LSB	Code = zero scale	4
Common-Mode Leakage Current	ICM	-1	0.01	1	µA	VW = VDD/2	4
Input Logic High	VIH	2.4			V	With respect to GND, VDD = 5 V	4
Input Logic Low	VIL			0.8	V	With respect to GND, VDD = 5 V	4
Input Logic High	VIH	2.1			V	With respect to GND, VDD = 3 V	4
Input Logic Low	VIL			0.6	V	With respect to GND, VDD = 3 V	4
Input Logic High	VIH	2			V	With respect to GND, VDD = +2.5 V, VSS = −2.5 V	4
Input Logic Low	VIL			0.5	V	With respect to GND, VDD = +2.5 V, VSS = −2.5 V	4
Output Logic High (SDO, RDY)	VOH	4.9			V	RPULL-UP = 2.2 kΩ to 5 V (see Figure 38)	4
Output Logic Low	VOL			0.4	V	IOL = 1.6 mA, VLOGIC = 5 V (see Figure 38)	4
Input Current	IIL	-1		1	µA	VIN = 0 V or VDD	4
Single-Supply Power Range	VDD	2.7		5.5	V	VSS = 0 V	5
Dual-Supply Power Range	VDD/VSS	2.25		2.75	V	Dual supply, ±VDD/VSS as printed	5
Positive Supply Current	IDD		2	5	µA	VIH = VDD or VIL = GND	5
Negative Supply Current	ISS	-4		-2	µA	VDD = +2.5 V, VSS = −2.5 V, VIH = VDD or VIL = GND	5
EEMEM Store Mode Current	IDD (store)			2	mA	VIH = VDD or VIL = GND, VSS = GND, ISS ≈ 0	5
EEMEM Store Mode Current	ISS (store)	-2			mA	VDD = +2.5 V, VSS = −2.5 V	5
EEMEM Restore Mode Current	IDD (restore)			320	µA	VIH = VDD or VIL = GND, VSS = GND, ISS ≈ 0	5
EEMEM Restore Mode Current	ISS (restore)	-320			µA	VDD = +2.5 V, VSS = −2.5 V	5
Power Dissipation	PDISS		10	30	µW	VIH = VDD or VIL = GND	5
Power Supply Sensitivity	PSS		0.006	0.01	%/%	ΔVDD = 5 V ± 10%	5
Clock Cycle Time	t1	20			ns		6
CS Setup Time	t2	10			ns		6
CLK Shutdown Time to CS Rise	t3	1			tCYC		6
Input Clock Pulse Width	t4, t5	10			ns	Clock level high or low	6
Data Setup Time	t6	5			ns	From positive CLK transition	6
Data Hold Time	t7	5			ns	From positive CLK transition	6
CS to SDO-SPI Line Acquire	t8			40	ns		6
CS to SDO-SPI Line Release	t9			50	ns		6
CLK to SDO Propagation Delay	t10			50	ns	RP = 2.2 kΩ, CL < 20 pF	6
CLK to SDO Data Hold Time	t11	0			ns	RP = 2.2 kΩ, CL < 20 pF	6
CS High Pulse Width	t12	10			ns		6
CS High to CS High	t13	4			tCYC		6
CS Rise to RDY Fall Time	t15		0.15	0.3	ms		6
Store EEMEM Time	t16		15	50	ms	Applies to Instructions 0x2, 0x3	6
Read EEMEM Time	t16		7	30	µs	Applies to Instructions 0x8, 0x9, 0x10	6
Preset Pulse Width (Asynchronous)	tPRW	50			ns		6
Endurance		1			MCycles	TA = 25°C	6
VDD to GND	VDD	-0.3		7	V		8
VSS to GND	VSS	-7		0.3	V		8
VDD to VSS	VDD−VSS			7	V		8
Terminal Current IA, IB, IW	IA, IB, IW	-20		20	mA	Pulsed	8
Terminal Current IA, IB, IW	IA, IB, IW	-2		2	mA	Continuous	8
Operating Temperature Range	TA	-40		85	°C		8
Maximum Junction Temperature	TJ max			150	°C		8
Storage Temperature Range	TSTG	-65		150	°C		8
Nominal End-to-End Resistance	RAB		25		kΩ	25 kΩ version (AD5235BRUZ25)	30
Resistance Temperature Coefficient	(ΔRAB/RAB)/ΔT × 10^6		35		ppm/°C		4
Voltage Divider Temperature Coefficient	(ΔVW/VW)/ΔT × 10^6		15		ppm/°C	Code = midscale	4
Junction-to-Ambient Thermal Resistance	θJA		150		°C/W	TSSOP-16	8
Junction-to-Case Thermal Resistance	θJC		28		°C/W	TSSOP-16	8

CAD (KiCad official)

Symbol: AD5235BRUZ25
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad5235bruz25-etched.step / ad5235bruz25-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5235bruz25.step / ad5235bruz25.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (32 pp, sha256 cfe1b2e773902141, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5235BRUZ25

Verified AD5235BRUZ25

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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