component

SN74AC574DWR

Public Made by Adom

by adom

Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74ac574dwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SN74AC574DWR

Texas Instruments · Flip Flops · SOIC-20-300mil

SN74AC574DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input; high places the eight outputs in the high-impedance state, low enables them, and it does not affect internal flip-flop operation.
2 1D input Data input for flip-flop 1, transferred to 1Q on the positive transition of CLK.
3 2D input Data input for flip-flop 2, transferred to 2Q on the positive transition of CLK.
4 3D input Data input for flip-flop 3, transferred to 3Q on the positive transition of CLK.
5 4D input Data input for flip-flop 4, transferred to 4Q on the positive transition of CLK.
6 5D input Data input for flip-flop 5, transferred to 5Q on the positive transition of CLK.
7 6D input Data input for flip-flop 6, transferred to 6Q on the positive transition of CLK.
8 7D input Data input for flip-flop 7, transferred to 7Q on the positive transition of CLK.
9 8D input Data input for flip-flop 8, transferred to 8Q on the positive transition of CLK.
10 GND power_in Ground pin.
11 CLK input Clock input; Q outputs take the logic levels at the D inputs on the positive transition.
12 8Q tri_state 3-state output of flip-flop 8, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
13 7Q tri_state 3-state output of flip-flop 7, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
14 6Q tri_state 3-state output of flip-flop 6, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
15 5Q tri_state 3-state output of flip-flop 5, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
16 4Q tri_state 3-state output of flip-flop 4, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
17 3Q tri_state 3-state output of flip-flop 3, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
18 2Q tri_state 3-state output of flip-flop 2, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
19 1Q tri_state 3-state output of flip-flop 1, rated for 24 mA high/low drive at VCC of 4.5 V to 5.5 V.
20 VCC power_in Supply voltage pin, 2 V to 6 V recommended operating range (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 2
Input voltage range VI -0.5 V max printed as VCC + 0.5 V 2
Output voltage range VO -0.5 V max printed as VCC + 0.5 V 2
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 2
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 2
Continuous output current IO -50 50 mA VO = 0 to VCC 2
Continuous current through VCC or GND ICC -200 200 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance θJA 58 °C/W DW package 2
Supply voltage VCC 2 6 V 3
High-level input voltage VIH 2.1 V VCC = 3 V 3
High-level input voltage VIH 3.15 V VCC = 4.5 V 3
High-level input voltage VIH 3.85 V VCC = 5.5 V 3
Low-level input voltage VIL 0.9 V VCC = 3 V 3
Low-level input voltage VIL 1.35 V VCC = 4.5 V 3
Low-level input voltage VIL 1.65 V VCC = 5.5 V 3
Input voltage VI 0 V max printed as VCC 3
Output voltage VO 0 V max printed as VCC 3
High-level output current IOH -12 mA VCC = 3 V 3
High-level output current IOH -24 mA VCC = 4.5 V 3
Low-level output current IOL 12 mA VCC = 3 V 3
Low-level output current IOL 24 mA VCC = 4.5 V 3
Input transition rise or fall rate Δt/Δv 8 ns/V 3
Operating free-air temperature TA -40 85 °C 3
High-level output voltage VOH 2.9 V IOH = −50 μA, VCC = 3 V 3
High-level output voltage VOH 4.4 V IOH = −50 μA, VCC = 4.5 V 3
High-level output voltage VOH 5.4 V IOH = −50 μA, VCC = 5.5 V 3
High-level output voltage VOH 2.46 V IOH = −12 mA, VCC = 3 V 3
High-level output voltage VOH 3.76 V IOH = −24 mA, VCC = 4.5 V 3
High-level output voltage VOH 4.76 V IOH = −24 mA, VCC = 5.5 V 3
Low-level output voltage VOL 0.1 V IOL = 50 μA, VCC = 3 V 3
Low-level output voltage VOL 0.44 V IOL = 12 mA, VCC = 3 V 3
Input current II -1 1 μA VI = VCC or GND, VCC = 5.5 V 3
Off-state output current IOZ -2.5 2.5 μA VO = VCC or GND, VCC = 5.5 V 3
Supply current ICC 40 μA VI = VCC or GND, IO = 0, VCC = 5.5 V 3
Input capacitance Ci 4.5 pF VI = VCC or GND, VCC = 5 V, TA = 25°C 3
Clock frequency fclock 60 MHz VCC = 3.3 V ± 0.3 V 4
Pulse duration, CLK high or low tw 7 ns VCC = 3.3 V ± 0.3 V 4
Setup time, data before CLK↑ tsu 3 ns VCC = 3.3 V ± 0.3 V 4
Hold time, data after CLK↑ th 1.5 ns VCC = 3.3 V ± 0.3 V 4
Clock frequency fclock 85 MHz VCC = 5 V ± 0.5 V 4
Pulse duration, CLK high or low tw 5 ns VCC = 5 V ± 0.5 V 4
Setup time, data before CLK↑ tsu 2 ns VCC = 5 V ± 0.5 V 4
Maximum frequency fmax 60 MHz VCC = 3.3 V ± 0.3 V 4
Propagation delay CLK to Q (low-to-high) tPLH 3.5 15 ns VCC = 3.3 V ± 0.3 V 4
Propagation delay CLK to Q (high-to-low) tPHL 3.5 13.5 ns VCC = 3.3 V ± 0.3 V 4
Output enable time OE to Q (to high) tPZH 2.5 12 ns VCC = 3.3 V ± 0.3 V 4
Output enable time OE to Q (to low) tPZL 3 11.5 ns VCC = 3.3 V ± 0.3 V 4
Output disable time OE to Q (from high) tPHZ 2.5 13 ns VCC = 3.3 V ± 0.3 V 4
Output disable time OE to Q (from low) tPLZ 1.5 10 ns VCC = 3.3 V ± 0.3 V 4
Maximum frequency fmax 85 MHz VCC = 5 V ± 0.5 V 4
Propagation delay CLK to Q (low-to-high) tPLH 2 11 ns VCC = 5 V ± 0.5 V 4
Propagation delay CLK to Q (high-to-low) tPHL 2 9.5 ns VCC = 5 V ± 0.5 V 4
Output enable time OE to Q (to high) tPZH 2 9 ns VCC = 5 V ± 0.5 V 4
Output enable time OE to Q (to low) tPZL 1.5 9 ns VCC = 5 V ± 0.5 V 4
Output disable time OE to Q (from high) tPHZ 1.5 10.5 ns VCC = 5 V ± 0.5 V 4
Output disable time OE to Q (from low) tPLZ 1 8.5 ns VCC = 5 V ± 0.5 V 4
Power dissipation capacitance Cpd 40 pF CL = 50 pF, f = 1 MHz, VCC = 5 V, TA = 25°C 4

CAD (KiCad official)

  • Symbol: SN74AC574DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74ac574dwr-etched.step / sn74ac574dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ac574dwr.step / sn74ac574dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 f19ddf1706af5db7, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF