component
LP2985IM5-2.5
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP2985IM5-2.5
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LP2985IM5-2.5 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply pin; use a capacitor of 1µF or larger from this pin to ground. |
| 2 | GND | power_in | Ground pin of the regulator. |
| 3 | ON/OFF | input | Enable pin: driving it high enables the device and driving it low disables it; tie to VIN if unused. |
| 4 | BYPASS | bidirectional | Bypass pin for low-noise performance; an external capacitor between BYPASS and ground reduces reference voltage noise. |
| 5 | VOUT | power_out | Regulator output; use a capacitor of 2.2µF or larger from this pin to ground, with nominal output capacitance greater than 2.2µF. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Continuous input voltage range (for legacy chip) | VIN | -0.3 | 16 | V | 4 | ||
| Continuous input voltage range (for new chip) | VIN | -0.3 | 18 | V | 4 | ||
| Output voltage range (for legacy chip) | VOUT | -0.3 | 9 | V | 4 | ||
| Output voltage range (for new chip) | VOUT | -0.3 | V | Max: VIN + 0.3 or 9 (whichever is smaller) | 4 | ||
| BYPASS pin voltage range (for new chip) | VBYPASS | -0.3 | 3 | V | 4 | ||
| ON/OFF pin voltage range (for legacy chip) | VON/OFF | -0.3 | 16 | V | 4 | ||
| ON/OFF pin voltage range (for new chip) | VON/OFF | -0.3 | 18 | V | 4 | ||
| Input - Output differential voltage (for legacy chip) | VIN, VOUT | -0.3 | 16 | V | 4 | ||
| Input - Output differential voltage (for new chip) | VIN, VOUT | -0.3 | 18 | V | 4 | ||
| Operating junction temperature | TJ | -55 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply input voltage (for legacy chip) | VIN | 3.1 | 16 | V | 4 | ||
| Supply input voltage (for new chip) | VIN | 2.5 | 16 | V | 4 | ||
| Output voltage (for legacy chip) | VOUT | 1.2 | 10 | V | 4 | ||
| Output voltage (for new chip) | VOUT | 1.2 | 5 | V | 4 | ||
| Enable voltage (for legacy chip) | VON/OFF | 0 | V | Max: VIN | 4 | ||
| Enable voltage (for new chip) | VON/OFF | 0 | 16 | V | 4 | ||
| Output current | IOUT | 0 | 150 | mA | 4 | ||
| Input capacitor | CIN | 1 | μF | 4 | |||
| Output capacitance (for legacy chip) | COUT | 2.2 | 4.7 | μF | 4 | ||
| Output capacitance (for new chip) | COUT | 1 | 2.2 | 200 | μF | 4 | |
| Output capacitor ESR (for new chip) | COUT ESR | 0 | 1 | Ω | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Output voltage tolerance (legacy chip, standard grade) | ΔVOUT | -1.5 | 1.5 | % | IL = 1 mA | 5 | |
| Output voltage tolerance (new chip) | ΔVOUT | -0.5 | 0.5 | % | IL = 1 mA | 5 | |
| Output voltage tolerance (legacy chip, standard grade) | ΔVOUT | -2.5 | 2.5 | % | 1 mA ≤ IL ≤ 50 mA | 5 | |
| Output voltage tolerance (legacy chip, standard grade) | ΔVOUT | -3 | 3 | % | 1 mA ≤ IL ≤ 150 mA | 5 | |
| Output voltage tolerance (legacy chip, standard grade) | ΔVOUT | -3.5 | 3.5 | % | 1 mA ≤ IL ≤ 50 mA, -40°C ≤ TJ ≤ 125°C | 5 | |
| Output voltage tolerance (new chip) | ΔVOUT | -1 | 1 | % | 1 mA ≤ IL ≤ 50 mA, -40°C ≤ TJ ≤ 125°C | 5 | |
| Output voltage tolerance (legacy chip, standard grade) | ΔVOUT | -4 | 4 | % | 1 mA ≤ IL ≤ 150 mA, -40°C ≤ TJ ≤ 125°C | 5 | |
| Line regulation (legacy chip) | ΔVOUT(ΔVIN) | 0.007 | 0.014 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V | 6 | |
| Line regulation (new chip) | ΔVOUT(ΔVIN) | 0.002 | 0.014 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V | 6 | |
| Line regulation (legacy chip) | ΔVOUT(ΔVIN) | 0.007 | 0.032 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C | 6 | |
| Line regulation (new chip) | ΔVOUT(ΔVIN) | 0.002 | 0.032 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C | 6 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 1 | 3 | mV | IOUT = 0 mA | 6 | |
| Dropout voltage (new chip) | VIN - VOUT | 1 | 2.75 | mV | IOUT = 0 mA | 6 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 7 | 10 | mV | IOUT = 1 mA | 6 | |
| Dropout voltage (new chip) | VIN - VOUT | 11.5 | 14 | mV | IOUT = 1 mA | 6 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 40 | 60 | mV | IOUT = 10 mA | 6 | |
| Dropout voltage (new chip) | VIN - VOUT | 98 | 115 | mV | IOUT = 10 mA | 6 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 120 | 150 | mV | IOUT = 50 mA | 6 | |
| Dropout voltage (new chip) | VIN - VOUT | 120 | 145 | mV | IOUT = 50 mA | 6 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 280 | 350 | mV | IOUT = 150 mA | 6 | |
| Dropout voltage (new chip) | VIN - VOUT | 180 | 198 | mV | IOUT = 150 mA | 6 | |
| GND pin current (legacy chip) | IGND | 65 | 95 | µA | IOUT = 0 mA | 6 | |
| GND pin current (new chip) | IGND | 69 | 95 | µA | IOUT = 0 mA | 6 | |
| GND pin current (legacy chip) | IGND | 850 | 1200 | µA | IOUT = 150 mA | 6 | |
| GND pin current (new chip) | IGND | 765 | 890 | µA | IOUT = 150 mA | 6 | |
| Peak output current (legacy chip) | IO(PK) | 300 | 350 | mA | VOUT ≥ VO(NOM) -5% (steady state) | 7 | |
| Peak output current (new chip) | IO(PK) | 300 | 350 | mA | VOUT ≥ VO(NOM) -5% (steady state) | 7 | |
| Short output current (legacy chip) | IO(SC) | 400 | mA | RL = 0 Ω (steady state) | 7 | ||
| Short output current (new chip) | IO(SC) | 375 | mA | RL = 0 Ω (steady state) | 7 | ||
| Junction-to-ambient thermal resistance (legacy chip, DBV SOT23-5) | RθJA | 205.4 | °C/W | 5 | |||
| Junction-to-ambient thermal resistance (new chip, DBV SOT23-5) | RθJA | 178.6 | °C/W | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is stron | 28 |
CAD (KiCad official)
- Symbol:
LP2985IM5-2.5 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lp2985im5-2-5-etched.step/lp2985im5-2-5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp2985im5-2-5.step/lp2985im5-2-5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
307d388652f2fc7d, retrieved 2026-11-05, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).