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Contents

README

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SN74HC192N

XBLW · Counters, Dividers · DIP-16

SN74HC192N from XBLW, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Data input 1 for asynchronous parallel load.
2 Q1 output Flip-flop output 1.
3 Q0 output Flip-flop output 0.
4 CPD input Count down clock input, LOW-to-HIGH edge triggered.
5 CPU input Count up clock input, LOW-to-HIGH edge triggered.
6 Q2 output Flip-flop output 2.
7 Q3 output Flip-flop output 3.
8 GND power_in Ground (0 V).
9 D3 input Data input 3 for asynchronous parallel load.
10 D2 input Data input 2 for asynchronous parallel load.
11 PL input Asynchronous parallel load input, active LOW.
12 TCU output Terminal count up (carry) output, active LOW.
13 TCD output Terminal count down (borrow) output, active LOW.
14 MR input Asynchronous master reset input, active HIGH.
15 D0 input Data input 0 for asynchronous parallel load.
16 VCC power_in Supply voltage.

Key specifications

Parameter Value
Manufacturer XBLW
Package DIP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HC192N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc192n-etched.step / sn74hc192n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc192n.step / sn74hc192n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (20 pp, sha256 32e9df0cd800f40d, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF