TPA3139D2RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUTPL	output	Class-D H-bridge positive output for left channel.
2	BSPL	passive	Bootstrap supply (BST) for positive high-side FET of the left channel.
3	PVCCL	power_in	Power supply for left channel H-bridge; right and left channel power supply inputs are connected internally.
4	SD/FAULT	bidirectional	TTL-level shutdown input with compliance to AVCC (LOW = outputs Hi-Z, HIGH = outputs enabled) that also reports faults (Over-Temp, Over-Current, DC Detect) by going Low, with auto-recovery once the fault is removed.
5	LINP	input	Positive audio input for left channel, biased at 2.5 V; connect to GND for PBTL mode.
6	LINN	input	Negative audio input for left channel, biased at 2.5 V; connect to GND for PBTL mode.
7	GAIN_SEL	input	Gain select input with TTL levels: Low = 20-dB gain, High = 26-dB gain, Floating = 26-dB gain.
8	MODE_SEL	input	Mode select input with TTL levels: Low = BD mode with UV threshold 7.5 V, High or Floating = 1SPW mode with UV threshold 3.4 V.
9	AVCC	power_in	Analog supply.
10	AGND	power_in	Analog signal ground.
11	GVDD	power_out	FET gate drive supply with nominal voltage of 5 V.
12	PLIMIT	input	Power limiter level control: connect a resistor divider from GVDD to GND to set the power limit, or connect directly to GVDD for no power limit.
13	RINN	input	Negative audio input for right channel, biased at 2.5 V.
14	RINP	input	Positive audio input for right channel, biased at 2.5 V.
15	MUTE	input	Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled), TTL logic levels with compliance to AVCC.
16	PVCCR	power_in	Power supply for right channel H-bridge; right and left channel power supply inputs are connected internally.
17	BSPR	passive	Bootstrap supply (BST) for positive high-side FET of the right channel.
18	OUTPR	output	Class-D H-bridge positive output for right channel.
19	PGND	power_in	Power ground for the H-bridges.
20	OUTNR	output	Class-D H-bridge negative output for right channel.
21	BSNR	passive	Bootstrap supply (BST) for negative high-side FET of the right channel.
22	BSNL	passive	Bootstrap supply (BST) for negative high-side FET of the left channel.
23	OUTNL	output	Class-D H-bridge negative output for left channel.
24	PGND	power_in	Power ground for the H-bridges.
25	Thermal Pad	power_in	Thermal pad; connect to GND for best thermal and electrical performance.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	Operational Amplifier/Comparator
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	3.5		14.4	V	PVCC, AVCC	6
High-level input voltage	VIH	2			V	SD/FAULT, MUTE, GAIN_SEL, MODE_SEL (max AVCC)	6
Low-level input voltage	VIL			0.8	V	SD/FAULT, MUTE, GAIN_SEL, MODE_SEL	6
Low-level output voltage	VOL			0.8	V	SD/FAULT, RPULL-UP =100 kΩ, PVCC = 14.4 V	6
High-level input current	IIH			50	µA	SD/FAULT, MUTE, GAIN_SEL, MODE_SEL, VI = 2 V, AVCC = 12 V	6
Low-level input current	IIL			5	µA	SD/FAULT, MUTE, GAIN_SEL, MODE_SEL, VI = 0.8 V, AVCC = 12 V	6
Operating free-air temperature	TA	-10		85	°C		6
Operating junction temperature	TJ	-10		150	°C		6
Supply voltage	AVCC, PVCC	-0.3		20	V	AVCC to GND, PVCC to GND	5
Input current				10	mA	To any pin except supply pins	5
Slew rate, maximum				10	V/ms	SD/FAULT to GND, GAIN_SEL, MODE_SEL, MUTE	5
Interface pin voltage		-0.3			V	SD/FAULT, GAIN_SEL, MODE_SEL, MUTE (max AVCC + 0.3 V)	5
Interface pin voltage PLIMIT		-0.3			V	PLIMIT (max GVDD + 0.3 V)	5
Interface pin voltage inputs		-0.3		5.5	V	RINN, RINP, LINN, LINP	5
Minimum load resistance	RL	4.8			Ω	BTL, 10 V ≤ PVCC ≤ 14.4 V	5
Minimum load resistance	RL	3.2			Ω	BTL, 3.5 V < PVCC < 10 V	5
Minimum load resistance	RL	2.4			Ω	PBTL, 10 V ≤ PVCC < 14.4 V	5
Minimum load resistance	RL	1.6			Ω	PBTL, 3.5 V ≤ PVCC < 10 V	5
Operating junction temperature range	TJ	-25		150	°C		5
Storage temperature range	Tstg	-40		125	°C		5
ESD HBM	V(ESD)	-1000		1000	V	Human body model, ANSI/ESDA/JEDEC JS-001	5
ESD CDM	V(ESD)	-250		250	V	Charged device model, JESD22-C101	5
Gain	G	19	20	21	dB	GAIN_SEL= 0.8 V	7
Gain	G	25	26	27	dB	GAIN_SEL= 2 V	7
Gate drive supply	GVDD	4.8	5	5.2	V	IGVDD = 2 mA	7
Oscillator frequency, Spread Spectrum ON	fOSC, SS	305		340	kHz	over operating free-air temperature range	8
Output offset voltage	/VOS/			1.5	mV	VI = 0 V	7
Quiescent supply current	ICC		20		mA	SD/FAULT = 2 V, ferrite bead filter, 1SPW Mode, PVCC = 12 V	7
Quiescent supply current	ICC		37		mA	SD/FAULT = 2 V, ferrite bead filter, BD Mode, PVCC = 12 V	7
Quiescent supply current in shutdown	ICC(SD)		10		µA	SD/FAULT = 0.8 V, no load	7
Drain-source on-state resistance high side	rDS(on)		180		mΩ	IO = 500 mA, TJ = 25°C, excluding metal and bond wire resistance	7
Drain-source on-state resistance low side	rDS(on)		180		mΩ	IO = 500 mA, TJ = 25°C, excluding metal and bond wire resistance	7
Maximum output current	IO		3.5		A	f = 1 kHz, RL = 3 Ω	7
Output power (BTL), 1% THD+N	PO		3		W	PVCC = 7.4 V, RL = 8 Ω, f = 1 kHz, 1SPW mode	7
Output power (BTL), 10% THD+N	PO		14.3		W	PVCC = 12 V, RL = 4 Ω, f = 1 kHz, BD mode	7
Total harmonic distortion + noise	THD+N		0.04		%	f = 1 kHz, PO = 5 W (half-power)	7
Power supply ripple rejection	PSRR		-85		dB	200-mVPP ripple at 1 kHz, inputs ac-coupled to GND	7
Signal-to-noise ratio	SNR		102		dB	Maximum output at THD+N < 1%, f = 1 kHz, A-weighted	7
Thermal trip point	OTE		150		°C		7
Thermal hysteresis			15		°C		7
Turn-on time	tON		15		ms	SD/FAULT = 2 V	7
Turn-off time	tOFF		2.9		µs	SD/FAULT = 0.8 V	7
DC detect time	tDCDET		800		ms	VRINP = 2.6 V and VRINN = 2.4 V, or VRINP = 2.4 V and VRINN = 2.6 V	7
Over Voltage Protection	OVP		15.8		V		7
Under Voltage Protection	UVP		7.5		V	MODE_SEL = 0.8 V (BD mode)	7
Under Voltage Protection	UVP		3.4		V	MODE_SEL = 2 V, or floating (1SPW mode)	7
Junction-to-ambient thermal resistance	RθJA		37.4		°C/W	RGE (QFN) 24 pins	6
Junction-to-case (top) thermal resistance	RθJC(top)		35.1		°C/W	RGE (QFN) 24 pins	6
Junction-to-board thermal resistance	RθJB		16.8		°C/W	RGE (QFN) 24 pins	6
Junction-to-top characterization parameter	ψJT		0.9		°C/W	RGE (QFN) 24 pins	6
Junction-to-board characterization parameter	ψJB		16.7		°C/W	RGE (QFN) 24 pins	6
Junction-to-case (bottom) thermal resistance	RθJC(bot)		7.3		°C/W	RGE (QFN) 24 pins	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalen	29

CAD (KiCad official)

Symbol: TPA3139D2RGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: tpa3139d2rger-etched.step / tpa3139d2rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpa3139d2rger.step / tpa3139d2rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (41 pp, sha256 38b48dcd30690fe8, retrieved 2026-10-31, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPA3139D2RGER

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