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AD9288BSTZ-40

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Analog Devices Analog To Digital Converters (ADC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD9288BSTZ-40

Analog Devices · Analog To Digital Converters (ADC) · LQFP-48(7x7)

AD9288BSTZ-40 from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground connection for the device.
2 AINA input Analog input for Channel A; the differential input range is ±512 mV p-p with a common-mode voltage of 0.3 × VD.
3 AINA input Complementary analog input for Channel A, used with pin 2 for differential operation with a ±512 mV p-p input range.
4 DFS input Data Format Select: offset binary output when set low and twos complement output when set high.
5 REFINA input Reference voltage input for Channel A; in normal operation it is strapped to REFOUT (pin 6) to use the internal reference.
6 REFOUT output Internal reference voltage output, a stable and accurate 1.25 V reference.
7 REFINB input Reference voltage input for Channel B; in normal operation it is strapped to REFOUT (pin 6) to use the internal reference.
8 S1 input User Select 1, which together with S2 sets the standby and data-align options per Table 4; tied with respect to VD.
9 S2 input User Select 2, which together with S1 sets the standby and data-align options per Table 4; tied with respect to VD.
10 AINB input Complementary analog input for Channel B, used with pin 11 for differential operation with a ±512 mV p-p input range.
11 AINB input Analog input for Channel B; the differential input range is ±512 mV p-p with a common-mode voltage of 0.3 × VD.
12 GND power_in Ground connection for the device.
13 VD power_in Analog supply, 3 V nominal (2.7 V to 3.6 V).
14 ENCB input Clock (Encode) input for Channel B; fully TTL/CMOS-compatible.
15 VDD power_in Digital supply, 3 V nominal (2.7 V to 3.6 V).
16 GND power_in Ground connection for the device.
17 D7B output Channel B digital output, MSB; TTL/CMOS-compatible and high impedance in standby.
18 D6B output Channel B digital output bit 6; TTL/CMOS-compatible and high impedance in standby.
19 D5B output Channel B digital output bit 5; TTL/CMOS-compatible and high impedance in standby.
20 D4B output Channel B digital output bit 4; TTL/CMOS-compatible and high impedance in standby.
21 D3B output Channel B digital output bit 3; TTL/CMOS-compatible and high impedance in standby.
22 D2B output Channel B digital output bit 2; TTL/CMOS-compatible and high impedance in standby.
23 D1B output Channel B digital output bit 1; TTL/CMOS-compatible and high impedance in standby.
24 D0B output Channel B digital output, LSB; TTL/CMOS-compatible and high impedance in standby.
25 NC unconnected Do not connect.
26 NC unconnected Do not connect.
27 GND power_in Ground connection for the device.
28 VDD power_in Digital supply, 3 V nominal (2.7 V to 3.6 V).
29 GND power_in Ground connection for the device.
30 VD power_in Analog supply, 3 V nominal (2.7 V to 3.6 V).
31 VD power_in Analog supply, 3 V nominal (2.7 V to 3.6 V).
32 GND power_in Ground connection for the device.
33 VDD power_in Digital supply, 3 V nominal (2.7 V to 3.6 V).
34 GND power_in Ground connection for the device.
35 NC unconnected Do not connect.
36 NC unconnected Do not connect.
37 D0A output Channel A digital output, LSB; TTL/CMOS-compatible and high impedance in standby.
38 D1A output Channel A digital output bit 1; TTL/CMOS-compatible and high impedance in standby.
39 D2A output Channel A digital output bit 2; TTL/CMOS-compatible and high impedance in standby.
40 D3A output Channel A digital output bit 3; TTL/CMOS-compatible and high impedance in standby.
41 D4A output Channel A digital output bit 4; TTL/CMOS-compatible and high impedance in standby.
42 D5A output Channel A digital output bit 5; TTL/CMOS-compatible and high impedance in standby.
43 D6A output Channel A digital output bit 6; TTL/CMOS-compatible and high impedance in standby.
44 D7A output Channel A digital output, MSB; TTL/CMOS-compatible and high impedance in standby.
45 GND power_in Ground connection for the device.
46 VDD power_in Digital supply, 3 V nominal (2.7 V to 3.6 V).
47 ENCA input Clock (Encode) input for Channel A; fully TTL/CMOS-compatible.
48 VD power_in Analog supply, 3 V nominal (2.7 V to 3.6 V).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-48(7x7)
Category Data Acquisition
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Minimum Conversion Rate 1 MSPS 25°C, Level IV 3
Encode Pulse Width High tEH 8 1000 ns 25°C, Level IV 3
Encode Pulse Width Low tEL 8 1000 ns 25°C, Level IV 3
Output Valid Time tV 2 3 ns Full VI; 10 pF ac load (footnote 2) 3
Output Propagation Delay tPD 4.5 6 ns Full VI; 10 pF ac load (footnote 2) 3
Logic 1 Voltage (digital inputs) 2 V Full VI 3
Logic 1 Current (digital inputs) -1 1 µA Full VI 3
Logic 0 Current (digital inputs) -1 1 µA Full VI 3
Digital Outputs Logic 1 Voltage 2.45 V Full VI 3
Gain Error -6 6 % FS 25°C, Level I 3
Gain Error -8 8 % FS Full VI 3
Gain Matching -1.5 1.5 % FS 25°C, Level V 3
Voltage Matching -15 15 mV 25°C, Level V 3
Input Voltage Range (with respect to AIN) -512 512 mV p-p Full V 3
Common-Mode Voltage (nominal 0.3 × VD) -0.2 0.2 V Full V; deviation about 0.3 × VD 3
Input Offset Voltage -35 35 mV 25°C, Level I 3
Input Offset Voltage -40 40 mV Full VI 3
Reference Voltage 1.2 1.25 1.3 V Full VI 3
Reference Tempco -130 130 ppm/°C Full VI 3
Gain Tempco 80 ppm/°C Full VI; ADC only with fixed 1.25 V external reference 3
Input Resistance 7 10 13 kΩ 25°C, Level I 3
Input Resistance 5 16 kΩ Full VI 3
Maximum Conversion Rate 40 MSPS Full VI 3
Digital Outputs Logic 0 Voltage 0.05 V Full VI 3
Logic 0 Voltage (digital inputs) 0.8 V Full VI 3
Differential Nonlinearity 1.25 LSB 25°C, Level I 3
Differential Nonlinearity 1.5 LSB Full VI 3
Integral Nonlinearity 1.25 LSB 25°C, Level I 3
Integral Nonlinearity 1.5 LSB Full VI 3
Power Dissipation 156 189 mW Full VI; fS = 100 MSPS, analog input -0.7 dBFS, both channels in operation 3
Standby Dissipation 6 11 mW Full VI; Encode clock in operation 3
Power Supply Rejection Ratio (PSRR) 8 20 mV/V 25°C, Level I 3
Supply Voltage VD, VDD (recommended) VD, VDD 2.7 3 3.6 V Single 3.0 V supply operation 1
Digital Output Supply (recommended) 2.5 3 3.6 V Digital outputs supply, interfacing with 3.3 V or 2.5 V logic 1
Reference Voltage Adjustment -5 5 % No appreciable degradation in performance when reference adjusted ±5% 14
VD, VDD (absolute maximum) VD, VDD 4 V 7
Analog Inputs (absolute maximum) -0.5 V Upper limit VD + 0.5 V 7
Digital Inputs (absolute maximum) -0.5 V Upper limit VDD + 0.5 V 7
VREF IN (absolute maximum) VREF IN -0.5 V Upper limit VD + 0.5 V 7
Digital Output Current (absolute maximum) 20 mA 7
Operating Temperature (absolute maximum) -55 125 °C 7
Storage Temperature (absolute maximum) -65 150 °C 7
Maximum Junction Temperature 150 °C 7
Maximum Case Temperature 150 °C 7
Thermal Impedance θja 57 °C/W 7

CAD (KiCad official)

  • Symbol: AD9288BSTZ-40
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9288bstz-40-etched.step / ad9288bstz-40-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9288bstz-40.step / ad9288bstz-40.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 881f700c9df1b8fd, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF