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LMK00334RTVT

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Texas Instruments Clock Buffers, Drivers, Distributors, WQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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LMK00334RTVT

Texas Instruments · Clock Buffers, Drivers, Distributors · WQFN-32-EP(5x5)

LMK00334RTVT from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground connection providing return path and thermal dissipation through PCB ground plane.
2 VCCOA power_in 3.3V or 2.5V ± 5% output buffer supply for group A requiring 0.1µF low ESR bypass capacitor.
3 CLKoutA0 output Differential HCSL clock output A0 (with CLKoutA0*) supporting DC to 400MHz with 50Ω termination.
4 CLKoutA0* output Differential HCSL clock output A0 complement (with CLKoutA0) supporting DC to 400MHz with 50Ω termination.
5 VCCOA power_in 3.3V or 2.5V ± 5% output buffer supply for group A requiring 0.1µF low ESR bypass capacitor.
6 CLKoutA1 output Differential HCSL clock output A1 (with CLKoutA1*) supporting DC to 400MHz with 50Ω termination.
7 CLKoutA1* output Differential HCSL clock output A1 complement (with CLKoutA1) supporting DC to 400MHz with 50Ω termination.
8 GND power_in Ground connection providing return path and thermal dissipation through PCB ground plane.
9 CLKout_EN input Low-active CMOS output enable for groups A and B with internal pull-down; logic low disables (Hi-Z), logic high enables HCSL outputs.
10 VCC power_in 3.3V ± 5% core and input buffer power supply (3.15V-3.45V) requiring 0.1µF low ESR bypass capacitor.
11 OSCin input Crystal or single-ended external clock input accepting 10-40MHz AT-cut crystals or 250MHz clock with 1pF input capacitance.
12 OSCout output Crystal oscillator output or leave floating if OSCin driven by single-ended external clock.
13 CLKin_SEL0 input CMOS clock input select control with internal pull-down for selecting CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin input.
14 CLKin0 input General-purpose clock input 0 (differential with CLKin0*) accepting LVPECL/LVDS/CML/SSTL or single-ended clock up to 400MHz with VID 0.15-1.3V.
15 CLKin0* input General-purpose clock input 0 complement (differential with CLKin0) accepting LVPECL/LVDS/CML/SSTL or single-ended clock up to 400MHz with VID 0.15-1.3V.
16 CLKin_SEL1 input CMOS clock input select control with internal pull-down for selecting CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin input.
17 GND power_in Ground connection providing return path and thermal dissipation through PCB ground plane.
18 CLKoutB1* output Differential HCSL clock output B1 complement (with CLKoutB1) supporting DC to 400MHz with 50Ω termination.
19 CLKoutB1 output Differential HCSL clock output B1 (with CLKoutB1*) supporting DC to 400MHz with 50Ω termination.
20 VCCOB power_in 3.3V or 2.5V ± 5% output buffer supply for group B requiring 0.1µF low ESR bypass capacitor.
21 CLKoutB0* output Differential HCSL clock output B0 complement (with CLKoutB0) supporting DC to 400MHz with 50Ω termination.
22 CLKoutB0 output Differential HCSL clock output B0 (with CLKoutB0*) supporting DC to 400MHz with 50Ω termination.
23 VCCOB power_in 3.3V or 2.5V ± 5% output buffer supply for group B requiring 0.1µF low ESR bypass capacitor.
24 GND power_in Ground connection providing return path and thermal dissipation through PCB ground plane.
25 NC unconnected Internally not connected pin that can be left floating or connected to any potential within -0.3V to (VCC+0.3)V.
26 CLKin1* input General-purpose clock input 1 complement (differential with CLKin1) accepting LVPECL/LVDS/CML/SSTL or single-ended clock up to 400MHz with VID 0.15-1.3V.
27 CLKin1 input General-purpose clock input 1 (differential with CLKin1*) accepting LVPECL/LVDS/CML/SSTL or single-ended clock up to 400MHz with VID 0.15-1.3V.
28 VCC power_in 3.3V ± 5% core and input buffer power supply (3.15V-3.45V) requiring 0.1µF low ESR bypass capacitor.
29 REFout output LVCMOS reference output providing clock copy enabled by REFout_EN high, supporting DC to 250MHz with CL ≤ 5pF.
30 VCCOC power_in 3.3V or 2.5V ± 5% REFout LVCMOS buffer supply requiring 0.1µF low ESR bypass capacitor.
31 REFout_EN input CMOS enable input with internal pull-down synchronous to selected clock; high enables REFout, low disables (Hi-Z).
32 VCC power_in 3.3V ± 5% core and input buffer power supply (3.15V-3.45V) requiring 0.1µF low ESR bypass capacitor.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Clock/Timing
Pins 33

CAD (KiCad official)

  • Symbol: LMK00334RTVT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lmk00334rtvt-etched.step / lmk00334rtvt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00334rtvt.step / lmk00334rtvt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 0fea59e58d9782db, retrieved 2026-09-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF